JPS59200425A - Treating method of semiconductor base body - Google Patents

Treating method of semiconductor base body

Info

Publication number
JPS59200425A
JPS59200425A JP7476183A JP7476183A JPS59200425A JP S59200425 A JPS59200425 A JP S59200425A JP 7476183 A JP7476183 A JP 7476183A JP 7476183 A JP7476183 A JP 7476183A JP S59200425 A JPS59200425 A JP S59200425A
Authority
JP
Japan
Prior art keywords
phosphorus
silicon wafer
silicon
wafer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7476183A
Other languages
Japanese (ja)
Inventor
Takashi Shimada
孝 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7476183A priority Critical patent/JPS59200425A/en
Publication of JPS59200425A publication Critical patent/JPS59200425A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To eliminate the partial injection of an impurity having gettering action while removing the remaining of a film, and to clean the surface of a base body by each diffusing the impurity to the first and second main surfaces of the base body, forming a protective layer on the second main surface and polishing the first main surface side until an impurity diffusion layer is removed. CONSTITUTION:With a silicon wafer 11, a wafer such as a lapped and chemical etching-finished wafer is used, phosphorus is diffused to both surface and back main surfaces of the silicon wafer 11, and N<+> type diffusion layers 13 are formed. Two layer structure of Si3N4 films and polycrystalline silicon films or protective layers 14 consisting of pure polycrystalline silicon films are deposited on both main surfaces of the silicon wafer 11 through a decompression CVD method. Said structure or layer may be deposited only on the back side through a normal pressure CVD method. One surface, the surface side, of the silicon wafer 11 is mirror-ground. The quantity of the surface side ground at that time shall be sufficient to completely remove the diffusion layer 14 of phosphorus.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はシリコンウェハ等の半導体基体の処理方法、特
にリン等によるゲッタリング飽理法に関するものである
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for processing semiconductor substrates such as silicon wafers, and in particular to a gettering saturation method using phosphorus or the like.

背景技術とその問題点 CCD固体撮像素子、 MOS−LSI(大規模集積回
路)、バイポーラIC等のシリコンデバイスの製造工程
に、おいては、シリコンウェハ自体の欠陥及び製造工程
中にシリコンウェハに導入される重金属汚染、結晶欠陥
等を低減する目的で、ゲッタリング兜埋をシリコンウェ
ハの裏面、内部に施している。ゲッタリング法としては
、サンドブラスト。
Background technology and its problems In the manufacturing process of silicon devices such as CCD solid-state image sensors, MOS-LSIs (large-scale integrated circuits), and bipolar ICs, defects in the silicon wafer itself and defects introduced into the silicon wafer during the manufacturing process are In order to reduce heavy metal contamination, crystal defects, etc., gettering embedding is performed on the backside and inside of silicon wafers. Sandblasting is the gettering method.

イオン注入、リン拡散等のゲッタリング(Extrin
sic Getter )と、結晶自体の酸素析出にと
もなう結晶内部の欠陥によるゲッタリング(Intri
nsic Getter )がある。この中ではゲッタ
リング効果として一瞥強く且つ持続性のあるリンゲッタ
リング法が用いられている。しかし、通常のリンゲッタ
リング法では、シリコンウェハ・の表面を保賎層で覆っ
て裏面にリンを拡散するとき、保護層のピンホール或は
リン拡散中のリンの異常拡散(メルトスルー)により表
面のシリコン中に局部的にリンが拡散される。例えばC
CD固体撮像素子ではこの局部的なリンの拡散が画像欠
陥の原因となる為に、この防止法が必要である。
Gettering (Extrin) such as ion implantation and phosphorus diffusion
sic Getter) and gettering (Intri) due to defects inside the crystal due to oxygen precipitation in the crystal itself.
nsic Getter). In this method, a ring gettering method is used which has a strong and persistent gettering effect. However, in the normal phosphorus gettering method, when the front surface of a silicon wafer is covered with a protective layer and phosphorus is diffused to the back surface, pinholes in the protective layer or abnormal diffusion (melt-through) of phosphorus during phosphorus diffusion occur. Phosphorus is locally diffused into the silicon on the surface. For example, C
In CD solid-state imaging devices, this local diffusion of phosphorus causes image defects, so a method for preventing this is necessary.

第1図はCCD固体撮像素子に用いられている従来のリ
ンゲッタリング処理方法の一例である。之は先づ、第x
vAAに示すように例えば(100)iflのP形シリ
コンウェハ(1)の表面にvノ拡散時の保護膜となる厚
さ1.0μm程度の5to2膜(2)を堆積する。
FIG. 1 is an example of a conventional ring-gettering processing method used in a CCD solid-state image sensor. This is first, number x
As shown in vAA, a 5to2 film (2) with a thickness of about 1.0 μm is deposited on the surface of a P-type silicon wafer (1) of (100) ifl, for example, to serve as a protective film during v diffusion.

このSi0g膜(2)のピンホール減少対策としてHC
t雰囲気中、1100℃の熱酸化による5toz展(厚
さ1800A)ト420℃f) eVD 5i02 w
A(Ji[サ8000A ) (1) 2層を堆積し、
シリコンクエバ(1)の裏面の5inz膜を除去してい
る。次に、第1図Bに示すようにシリコンウェハ(1)
の裏面にリンを拡散してリン拡散層(8)を形成する。
As a measure to reduce pinholes in this Si0g film (2), HC
5toz expansion (thickness 1800A) by thermal oxidation at 1100℃ in t atmosphere (420℃f) eVD 5i02 w
A (Ji[Sa8000A) (1) Deposit two layers,
The 5inz film on the back side of the silicon cube (1) is removed. Next, as shown in FIG. 1B, a silicon wafer (1) is
A phosphorus diffusion layer (8) is formed by diffusing phosphorus on the back surface of the substrate.

従来工程では1100℃、60分のリン拡散を行い、表
面濃度がl X 1g”i3以上になっている。
In the conventional process, phosphorus diffusion was performed at 1100° C. for 60 minutes, and the surface concentration was greater than 1×1 g”i3.

次に第1図Cに示すようにリンのウェハ光面への外部拡
散を防止する為に、5isN4膜(厚さ600A程度)
と純粋な多結晶シリコン族(厚さ250OA程度)の保
護層(4)を堆積する。この保護層(4)は減圧CVD
法を用いると両面に堆積する。次に、第1図りに示すよ
うにシリコンウェハ(1)の表面に堆積された保護層(
4)及び5i02J[(2)をエツチング除去してシリ
コン表面(la)を臨ます。
Next, as shown in FIG.
Then, a protective layer (4) of pure polycrystalline silicon family (about 250 OA thick) is deposited. This protective layer (4) was formed by low pressure CVD.
When using this method, it is deposited on both sides. Next, as shown in the first diagram, a protective layer (
4) and 5i02J [(2) are etched away to expose the silicon surface (la).

しかるに、かかる従来のリンゲッタリング処理方法にお
いては、次の様な問題点があった。まず、リン拡散を行
う際のウニ八表面の8102膜(2)のピンホールが問
題である。5i02膜(2)を一層構造とじた場合には
膜厚と共にピンホールは減少するも0″′/、2磐 一部にはならない。さらに熱酸化(HCt雰囲気中)に
よる5in2膜とCVD5i02の2層構造にしてもピ
ンホールは完全になくならない。またリン拡散時の5i
02膜(2)にピンホールがなくても、リン拡散時に5
in2膜(2)の表面にリンの粉末等が付着してメルト
スルーの様な異常拡散を生じることがある。従ってマス
ク効果のある保護膜の選択が重要となるが、適当なもの
がないのが現状である。また、第1図りの工程では、ウ
ニ八表面側の保護層(4)及び5i02膜(2)を全面
完全に除去する必要があるが、保護層(4)を構成シる
Si3N4腰及び多結晶シリコン膜の膜厚の不均一性や
ごみにより一部局部的に残ることがある。5i02 !
(2)も同様なことがある。また膜を堆積し、除去する
工程が増加するとシリコン表面の清浄度を保つことが困
難となり、従ってこのような工程の増加は出来るだけ避
けたいところである。さらに、従来工程ではリンゲッタ
リング処理の為に8工程必要であり、工程が長くなる。
However, such conventional ring-gettering processing methods have the following problems. First, there is a problem with the pinholes in the 8102 film (2) on the surface of the sea urchin when performing phosphorus diffusion. When the 5i02 film (2) is formed into a single layer structure, the pinholes decrease as the film thickness increases, but they do not become 0″'/2. Even with a layered structure, pinholes cannot be completely eliminated.Also, 5i during phosphorus diffusion
Even if there are no pinholes in the 02 membrane (2), 5
Phosphorus powder or the like may adhere to the surface of the in2 film (2), causing abnormal diffusion such as melt-through. Therefore, it is important to select a protective film that has a masking effect, but at present there is no suitable protective film. In addition, in the step of the first plan, it is necessary to completely remove the protective layer (4) and the 5i02 film (2) on the surface side of the sea urchin, but it is also necessary to completely remove the protective layer (4) on the surface side of the sea urchin. Some parts may remain locally due to non-uniformity in the thickness of the silicon film or dust. 5i02!
(2) may also be similar. Furthermore, as the number of steps for depositing and removing films increases, it becomes difficult to maintain the cleanliness of the silicon surface, so it is desirable to avoid increasing the number of steps as much as possible. Furthermore, in the conventional process, eight steps are required for the ring gettering process, making the process longer.

以上の様な原因により現実のCCD固体撮像素子では、
工程改善の努力を行っても完全な方法はなく、リンのと
び込みによる白黒点、5i02膜、Si3N4膜等の残
りによるパターン欠陥が発生していた。
Due to the above reasons, in actual CCD solid-state image sensors,
Despite efforts to improve the process, there is no perfect method, and pattern defects occur due to black and white dots due to phosphorus penetration, and residual 5i02 film, Si3N4 film, etc.

発明の目的 本発明は上述のような欠点を解消した半導体基体の処理
方法を提供するものである。
OBJECTS OF THE INVENTION The present invention provides a method for processing semiconductor substrates that eliminates the above-mentioned drawbacks.

発明の概要 本発明は、半導体基体の第1及び第2主面に夫々ゲッタ
作用のある不純物を拡散し、少なくとも第2主面上に保
護層を形成して後、基体の第1主面側を上記不純物の拡
散層が除去されるまで研磨する。この発明のゲッタリン
グ処理方法では、不純物の局部的なとび込みがない上に
、膜の残りもなく、半導体基体の表面が清浄になる。
SUMMARY OF THE INVENTION The present invention involves diffusing impurities having a getter function into the first and second main surfaces of a semiconductor substrate, forming a protective layer on at least the second main surface, and then dispersing the impurities on the first main surface side of the substrate. is polished until the impurity diffusion layer is removed. In the gettering treatment method of the present invention, there is no local penetration of impurities, and there is no remaining film, resulting in a clean surface of the semiconductor substrate.

゛   実施例 以下、第2図を参照して本発明の実施例について説明す
る。
゛ Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIG.

本例においては、半導体基体例えば(100)面のP形
7リコンウエハ(11)を用意する。この場合、シリコ
ンウェハ住υはラップし、ケミカルエツチング仕上げの
ウェハを用いる。片面鏡面研磨した通常のウェハを用い
てもよいが、再度鏡面研磨することになるので、両面ケ
ミカルエツチング仕上げの方がコスト的に有利である。
In this example, a semiconductor substrate, for example, a P-type 7 silicon wafer (11) having a (100) plane is prepared. In this case, the silicon wafer is wrapped and finished with chemical etching. An ordinary wafer with mirror polishing on one side may be used, but since mirror polishing is required again, chemical etching finish on both sides is more cost-effective.

鏡面研磨前のシリコンウェハを用いる為にシリコンウエ
ノ)の厚さをま研磨量分だけ厚くしておく必要がある。
In order to use a silicon wafer before mirror polishing, it is necessary to increase the thickness of the silicon wafer by the amount of polishing.

例えは3インチのウェハは、最終仕上げの厚さか400
μmなので450μm前後にしておく必要がある。
For example, a 3-inch wafer has a final finishing thickness of 400 mm.
Since it is μm, it needs to be around 450 μm.

而して、第2図Aに示すようにこのシリコンウェハαυ
の表裏側主面にリンを拡散してN形拡散層住騰を形成す
る。
Therefore, as shown in FIG. 2A, this silicon wafer αυ
Phosphorus is diffused on the front and back main surfaces to form an N-type diffusion layer.

次に、第2図Bに示すよう、、にシリコンウェハ劃υの
両生面上に減圧CVD法によってSi3N4腺と多結晶
シリコン膜の2層構造あるいは純粋な多結晶シリコン膜
による保護層(14)を堆積する。なお、常圧CVD法
では裏面側だけに堆積すれはよい。
Next, as shown in FIG. 2B, a protective layer (14) made of a two-layer structure of Si3N4 glands and a polycrystalline silicon film or a pure polycrystalline silicon film is formed by low pressure CVD on both sides of the silicon wafer. Deposit. Note that in the normal pressure CVD method, it is good to deposit only on the back side.

次で、第2図Cに示すようにシリコンウエノSaυの片
面即ち表面側を鏡面研磨する。このときの研磨量はリン
の拡散層α尋を十分除去するにたる量で  −ある。
Next, as shown in FIG. 2C, one side, that is, the front side of the silicon wafer Saυ is mirror-polished. The amount of polishing at this time is sufficient to sufficiently remove the phosphorus diffusion layer α.

かかるリンゲッタリング処理法によれば、シリコンウェ
ハ(Lυの両主面にリンを拡散し、さらに保賎層(14
)を堆積した後に、表面側をリンの拡散層a31が除去
されるまで鏡面研磨するので、本質的に従来の如きリン
の局部的なとび込みがなくなり、また8i02 、 S
i3N4等の膜の残りもなく、清浄なシリコン表面が得
られる。また工程を簡略化することができ、歩留りの向
上を図ることができる。従って、CCD固体撮像素子に
適用した場合、リンのとび込みによる白黒点、5i02
 、 Si3N4等の膜の残りによるパターン欠陥の発
生はなくなる。
According to such a phosphorus gettering treatment method, phosphorus is diffused on both main surfaces of a silicon wafer (Lυ), and a protective layer (14
) is deposited, the surface side is mirror-polished until the phosphorus diffusion layer a31 is removed, which essentially eliminates the local penetration of phosphorus as in the conventional method, and 8i02, S
A clean silicon surface is obtained without any residual film such as i3N4. Further, the process can be simplified and the yield can be improved. Therefore, when applied to a CCD solid-state image sensor, a black and white point due to phosphorus penetration, 5i02
, pattern defects caused by remaining films such as Si3N4 are eliminated.

尚、上側ではゲッタ作用のある不純物としてリンを用い
たが、リン以外の不純物でも良い。
Although phosphorus was used as an impurity having a getter effect on the upper side, impurities other than phosphorus may be used.

本発明の基本構成は上述の如くであるが、実施に際して
は次の2点に注意する必要がある。1つは鏡面研磨後に
観察される積層欠陥であり、もう1つはスリップライン
の発生である。本発明ではリン拡散を行った後、シリコ
ン表面を研磨してシリコン表面を表面として使用する。
Although the basic configuration of the present invention is as described above, it is necessary to pay attention to the following two points when implementing it. One is stacking faults observed after mirror polishing, and the other is the occurrence of slip lines. In the present invention, after performing phosphorus diffusion, the silicon surface is polished and used as a surface.

通常用いられているC2結晶で本処理方法を行うと、シ
リコン結晶中の酸素濃度が高い為にリン拡散時(基本的
には酸化しても同じ)にシリコン中の酸素が析出をおこ
し、欠陥核あるいは積層欠陥の核となる。この析出はシ
リコン中の酸素濃度に依存し酸素濃度が高い程析出量が
多くなる。この為に本発明に用いるシリコンウェハIは
酸素濃度が低く制御されたものを使用する必要がある。
If this treatment method is applied to a commonly used C2 crystal, the oxygen in the silicon will precipitate during phosphorus diffusion (basically the same even when oxidized) due to the high oxygen concentration in the silicon crystal, causing defects. It becomes the nucleus or the nucleus of a stacking fault. This precipitation depends on the oxygen concentration in silicon, and the higher the oxygen concentration, the greater the amount of precipitation. For this reason, it is necessary to use a silicon wafer I used in the present invention whose oxygen concentration is controlled to be low.

使用するシリコンウェハQl)17)酸素濃度ハロx1
017crIV3〜10×101瞥3ノ範囲が好ましい
Silicon wafer used Ql) 17) Oxygen concentration halo x1
A range of 017crIV3 to 10×101 eyes 3 is preferable.

第3図はシリコン中の酸素濃度と積層欠陥密度について
の実験結果を示す。測定は、リン拡散温度を1100℃
とした第2図A−Cの工程後、さらに1100℃の熱酸
化を行った後に測定した。積層欠陥の観察はセツコ・エ
ツチング(5ecco Etching )後に行った
。なお、酸素濃度を制御する結晶成長法としては、容器
内のシリコン表面に静磁場を印加し、容器と相対的に回
転するようにしてシリコン結晶体を引上げ、容器からシ
リコン融液中への酸素の溶解を制御する結晶成長法を用
覧・・ており−1本実験ではこれによって得られたシリ
コンウェハを用いて行った。
FIG. 3 shows experimental results regarding the oxygen concentration in silicon and the stacking fault density. The measurement was performed at a phosphorus diffusion temperature of 1100°C.
After the steps shown in FIG. 2A to C, the measurement was carried out after further thermal oxidation at 1100°C. Stacking faults were observed after 5ecco etching. In addition, as a crystal growth method to control the oxygen concentration, a static magnetic field is applied to the silicon surface in the container, and the silicon crystal is pulled up while rotating relative to the container. This experiment was conducted using a silicon wafer obtained by this method.

この第3図から積層欠陥が0cIn  となる酸素#に
度は約7.0X10 cm  以下である。また、スリ
ップラインは1100℃の熱酸化では1xlOcIn 
以上の酸素濃度で発生しなくなる。この実験からウェハ
プロセス温度が1100℃では適当な条件がなく、温度
を1050℃以下にする必要がある。またリンゲッタリ
ング効果の点からはリン拡散温度が高いほど効果が強く
且つ持続性がある。その為にリン拡散の温度が高い方が
良いが拡散時間な長(することによっである程度カバー
できる。CCD撮像素子の試作では、リン拡散として1
000℃、120分を用いており、リンゲッタリング効
果も1100℃より若干低いようではあるが、デバイス
特性上の差は見い出されていない。
From FIG. 3, the oxygen concentration at which the stacking fault becomes 0 cIn is about 7.0×10 cm or less. In addition, the slip line is 1xlOcIn for thermal oxidation at 1100°C.
It will no longer be generated at higher oxygen concentrations. From this experiment, there are no suitable conditions for a wafer process temperature of 1100°C, and it is necessary to lower the temperature to 1050°C or lower. In addition, from the point of view of the phosphorus gettering effect, the higher the phosphorus diffusion temperature, the stronger and more durable the effect. For this reason, it is better to have a higher temperature for phosphorus diffusion, but this can be covered to some extent by increasing the diffusion time.
000° C. for 120 minutes, and the ring gettering effect seems to be slightly lower than that of 1100° C., but no difference in device characteristics has been found.

1000℃の熱処理では第3図の積層欠陥発生の臨界酸
素濃度はlX10 crn 以上となり、スリップライ
ンの発生は6X10  cm  以下となる。さらに熱
処理温度を下げればこの範囲は広がる傾向があるが、現
状のウェハプロセスでは1000”C前後の温度であり
、またリンゲッタ効果の点からはリン拡散が1000℃
以下ではゲッタリング効果が不十分になると考えられる
In heat treatment at 1000° C., the critical oxygen concentration for generating stacking faults as shown in FIG. 3 becomes 1×10 crn or more, and the occurrence of slip lines becomes 6×10 cm or less. This range tends to widen if the heat treatment temperature is further lowered, but in the current wafer process, the temperature is around 1000"C, and from the point of view of the ring getter effect, phosphorus diffusion is 1000"C.
It is thought that the gettering effect will be insufficient below.

本例で用いたシリコン中の酸素濃度は赤外測定1 1110on  の吸収ピークの吸収係数α(Crn)
と濃度7 (Oi)との換算係数を4.81X10  αを用いて
いる。
The oxygen concentration in the silicon used in this example is determined by the absorption coefficient α (Crn) of the absorption peak of 1110 on infrared measurement.
A conversion factor of 4.81×10 α is used for the conversion coefficient between the concentration and the concentration 7 (Oi).

発明の効果 上述せる本発明のゲッタリング処理方法によれば、不純
物の局部的なとび込みがない上に、膜の残りもな(、清
浄な半導体基体表面が得られる。
Effects of the Invention According to the gettering treatment method of the present invention described above, not only is there no local penetration of impurities, but also a clean semiconductor substrate surface is obtained with no remaining film.

また、工程が簡略化され、歩留りが向上する。従って、
CCD固体撮像素子、 MOS−LSI 、バイポーラ
IC等の半導体デバイスの製造に適用して好適ならしめ
るものである。
Moreover, the process is simplified and the yield is improved. Therefore,
It is suitable for application to the manufacture of semiconductor devices such as CCD solid-state image sensors, MOS-LSIs, and bipolar ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A−Dは従来のゲッタリング処理方法の例を示す
工程図、第2図A〜Cは本発明にょるゲッタリング地理
方法の例を示す工程図、第3図はシリコン中の酸素濃度
と積層欠陥@度の関係を示す特性図である。 (1)(lυはシリコンウェハ、(3)(lal&! 
リン拡散層、(4)Q引ま保獲層である。 第2図 第8図
1A-D are process diagrams showing an example of a conventional gettering processing method, FIGS. 2A-C are process diagrams showing an example of a gettering geographical method according to the present invention, and FIG. FIG. 2 is a characteristic diagram showing the relationship between concentration and stacking fault degree. (1) (lυ is silicon wafer, (3) (lal&!
(4) a phosphorus diffusion layer and a Q-retention layer. Figure 2 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 半導体基体の第1及び第2主面に夫々ゲッタ作用のある
不純物を拡散する工程と、少なくとも前記第2主面上に
保護層を被着形成する工程と、前記基体の第1主面を前
記不純物の拡散層が除去されるまで研磨する工程を有し
て成る半導体基体の処理方法。
a step of diffusing an impurity having a gettering effect into the first and second main surfaces of the semiconductor substrate, a step of depositing a protective layer on at least the second main surface, and a step of depositing a protective layer on at least the second main surface; A method for processing a semiconductor substrate comprising the step of polishing until an impurity diffusion layer is removed.
JP7476183A 1983-04-27 1983-04-27 Treating method of semiconductor base body Pending JPS59200425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7476183A JPS59200425A (en) 1983-04-27 1983-04-27 Treating method of semiconductor base body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7476183A JPS59200425A (en) 1983-04-27 1983-04-27 Treating method of semiconductor base body

Publications (1)

Publication Number Publication Date
JPS59200425A true JPS59200425A (en) 1984-11-13

Family

ID=13556578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7476183A Pending JPS59200425A (en) 1983-04-27 1983-04-27 Treating method of semiconductor base body

Country Status (1)

Country Link
JP (1) JPS59200425A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2680606C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method of manufacture of semiconductor structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2680606C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method of manufacture of semiconductor structures

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