JPS61120398A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a redundancy circuit even to a high-speed storage device such as a bipolar type memory device and to improve the manufacture yield of the storage device by providing a comparing gate circuit which compares readout data of a defective circuit part with input address data directly, and switching the defective circuit part to the redundancy circuit part when access to the defective circuit part is detected. CONSTITUTION:A word address W-ADD is applied to the comparing gate 10 as well as compared with address data which is supplied from a PROM9 stored with the address of the redundancy circuit part and indicates the defective circuit part. Consequently, when both addresses coincide with each other, a selection signal SR is outputted and applied to word drivers 3 and 8. The word driver 3 when applied with the selection signal is inhibited to intercept the word line selection signal of a memory cell array 1, and the redundancy word driver 8 inputs a word line selection signal to a redundancy memory cell array 7 by being applied with the selection signal SR. Consequently, the redundancy memory cell array 7 is selected to write and read data in and out of the memory cell array 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that has a redundant circuit section to be used in place of a defective circuit section such as a defective memory cell, and that has an input address. 4. A semiconductor memory in which switching between a defective circuit portion and a redundant circuit portion is performed by directly comparing the address of the defective circuit portion. Regarding q device.

(Prior Art) FIG. 4 schematically shows a conventional random access memory device. The memory device in the figure has a word line WL and a bit line B.
A memory cell array 1 having memory cells each connected to L, an address buffer 2 for word addresses, a word driver 3, and an address buffer 4 for bit addresses.
, a bit driver 5, an input/output circuit 6 including a sense amplifier and a write amplifier.

In the memory device of FIG. 4, when the write enable signal WE is at a high level, for example, the write mode is entered, and the memory cell corresponding to word address -ADD and bit address low 800 is selected, and the memory cell Data is written to. That is, the word address W-A
DD is input to a decoder (not shown) via the address buffer 2, and a word line selection signal is generated. and,
The word driver 3 drives the selected word line based on this word line selection signal. Similarly, the bit address row 800 is manually input to a decoder (not shown) via the address buffer 4. Then, the bit line selection signal generated by the decoder is input to the bit driver 5, and the selected bit line is driven. Write data Din is input to the thus selected word line WL and bit line BL via the write amplifier in the input/output circuit 6, and data is written. In the case of data reading, the write enable signal WE is set to a low level, for example, and the word line WL and bit line BL are selected by the word address 800 and bit address B-ADD as in the case of writing. Information of the memory cells connected to the word line WL and bit line BL selected in this way is amplified by the sense amplifier in the input/output circuit 6 and output as read data Dout.

However, in the conventional memory devices as described above, especially in the case of high-speed memory devices such as bipolar memory devices, redundant memory cells and the like are not provided. Therefore, for example, if a certain memory cell in the memory cell array 1 or a word driver unit connected to a certain word line is defective, the memory device itself becomes a defective product and the manufacturing yield of semiconductor memory devices can be increased. There was an inconvenience that it was not possible.

(Problems to be Solved by the Invention) In view of the above-mentioned problems with the conventional type, the present invention enables switching between a defective circuit portion and a redundant circuit portion to be performed at high speed in a semiconductor memory device, and for example, a bipolar It is an object of the present invention to enable a redundant circuit portion to be provided even in a high-speed memory device such as a type memory device, and to increase the manufacturing yield of the memory device.

(Means for Solving the Problems) In the semiconductor memory device according to the present invention, there is provided a read-only memory that stores the address of a defective circuit portion, such as a word line including a defective memory cell, and read data and input of the read-only memory. A comparison gate circuit is provided to directly compare address data, and if it is detected by the output of this comparison gate circuit that a defective circuit section is about to be accessed, a redundant circuit section is accessed in place of the defective circuit section. The circuit is switched so that the

(Function) By using the above-mentioned means, the manual address is directly compared with the address of the defective circuit part stored in the one-hand only memory, so that a switching signal for accessing the redundant circuit part, that is, redundant circuit selection is generated. It becomes possible to extremely reduce signal delay time, and selection of redundant circuits can be performed without affecting access time etc. even in high-speed memory devices such as bipolar memory devices.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a semiconductor memory device according to an embodiment of the present invention. The memory device shown in the figure is configured to switch between a defective circuit section and a redundant circuit section in units of word lines, for example, and has a memory cell array l, a word address address, a couch 2, a word driver 3, etc. To,
A programmable read-only memory (hereinafter simply FR
OM) 9, and the input word address -ADD
A comparison gate 10 is provided for comparing the read data of the f'ROM 9 and the read data of the f'ROM 9. Note that, in FIG. 1, illustrations of a bit address address buffer, a bit driver, an input/output circuit, etc. are omitted. Further, a similar configuration is used when switching redundant circuits on a bit line basis.

In the storage device shown in FIG. 1, when a write or read operation is performed, a bit address is added to an address buffer (not shown) for bit addresses, and a word address W-ADD is added to address buffer 2 for word addresses. is input.

Word address W-ADD in address buffer 2
is amplified and amplified to a predetermined level and decoded to generate a word line selection signal, which is input to the word driver 3. At this time, if the redundant circuit selection signal SR is not applied from the comparison gate 10, the word line selection signal is applied to the word line of the memory cell array l, and a predetermined word line is selected, as shown in FIG. A write or read operation is performed in the same manner as in a storage device.

The word address 1 to 00 is also applied to comparison gate 10 and is compared with address data from FROM 9 indicating a defective circuit portion, such as a defective word. As a result of the comparison, if both addresses do not fail, the redundant circuit selection signal SR is not output, but if the two match, the selection signal SR is output and applied to each word driver 3 and 8. . The word driver 3 is inhibited when the selection signal SR is applied, and the word line selection signal of the memory cell array I is cut off. In contrast, the redundant word
1 driver 8 inputs a word line selection signal to redundant memory cell array 7 by applying selection signal SR.

As a result, the redundant memory cell array 7 is selected, and data is written to or read from the memory cell array 7. The signal path indicated by the dotted line 2 in FIG. 1 is for writing the address of the defective circuit portion into the FROM 9.

That is, for example, when a defective memory cell is detected by an operation test in a wafer state, the address -^DO of the word containing the defective memory cell is written to FROM 9 in response to application of the write signal WT.

FIG. 2 shows a detailed configuration of the storage device shown in FIG. 1. Second
In the figure, the memory cell array 1 has a high voltage side word line W
L+ and low voltage side word line WL- and bit lines BL and BL
A plurality of memory cells MC are connected between the memory cells MC and MC. Memory cell MC is 2, for example, PNP type transistor Q
1. Q2 and NPN multi-emitter transistor Q
3. It is a flip-flop type with Q4. Further, a constant current circuit ISI is connected between the low voltage side word line WL- and the low voltage side power supply terminal Vee. each high pressure side,
The word line WL+ is connected to a word driver unit 11 having transistors Q5, Q6, and Q7 whose emitters are commonly connected, a constant current circuit S2, a load resistor R1, and a driver transistor Q8. An address buffer unit 12 and a comparison gate unit 13 are provided for each bit of word address W-ADD.

The address buffer unit 12 includes a transistor Q8,
An input limiter follower having a diode D1 and a constant current circuit 133, and a transistor Q9. QIO8 constant current circuit IS4, load resistors R2, R3, and diode D
2 and a current switch circuit. The output of address buffer unit 12 is connected to word decoder 14. The word decoder 14 is inserted between a decoder line 15 consisting of a plurality of signal lines, a plurality of constant voltage FI sources RS15 connected to each signal line, and each output of the address buffer unit 12 and the decoder line 15. A multi-emitter transistor Qll is provided. In addition,
In FIG. 2, only one of the outputs of the address buffer unit 12, the multi-emitter transistor Q11 connected to the collector of the transistor QIO, is shown, but in reality, the collector of the transistor Q9 and the decoder line 15 are shown. Transistors corresponding to the transistor Qll are also provided between the address buffer units of other bits and the decoder 5sis. The emitter of each of these multi-emitter transistors is connected to each signal line of the decoder line 15 as appropriate. Further, the bases of each transistor Q5 and Q6 of the word driver unit 11 are also connected to the decoder vA1.
It is connected to the No. 5 signal line.

Comparison gate circuit unit 13 uses word address -AD
A transistor Q12 is provided corresponding to each bit of D.
, Q13,--9Q18, constant current circuit IS5゜I
It is composed of S6, rs7, IS8, diode D3, resistors R4, R5, R6, etc. The outputs of the comparison gate units corresponding to each bit are connected together and connected to the base of the transistor Q7 of the word driver unit 11 and the input of a redundant word driver, which will be described later, to supply a redundant circuit selection signal SR.

The redundant word driver 16 includes transistors Q19 . Q20, constant current circuit IS9, load resistance R
7 and a driver transistor Q21. The output or emitter of driver transistor Q21 is connected to high voltage side word line WL(R)1 of redundant memory cell array 7. A memory cell MC is connected between the high-voltage side word line (R) 10 and the low-voltage side word line WL (R)-, and the low-voltage side word line -[, (1?)- is connected to a current discharge cell. A constant current circuit l5IO is connected.

Note that each bit line is provided in common to the memory cell array l and the redundant memory cell array 7.

In FIG. 2, 17 is an address buffer for bit addresses, 18 is a bit address decoder, and 19 is a bit driver, which is a multi-emitter transistor Q.
22. Q23, a transistor Q24, and constant current circuits 1511, rs12, and 1513. Further, 20 is a sense amplifier, which connects each bit line BL and B via transistors Q25 and Q26.
Connected to LB. A chip select buffer 21 activates each circuit in response to a chip select signal C8.

Reference numeral 22 denotes a read/write control circuit and a write amplifier, which drive each bit line BL and BLB via transistors Q27 and Q2B.

In the semiconductor memory device having the above configuration, when writing and reading operations are performed, the word address -ADD and the bit address B-ADD are applied, and the chip select signal C3 is set to a high level, for example. Further, the write enable signal WE is set to a high level and a low level, respectively, in accordance with write and read operations. Depending on the level of each bit of word address -ADD, a high level or low level signal is applied from each address buffer 12 to each signal line of decoder line 15 via multi-emitter transistor Ql1 and the like.

Each signal line of the decoder line 15 is connected to a plurality of multi-emitter transistors, and if at least one of the outputs of these multi-emitter transistors is at a high level, the signal line also becomes at a high level. Then, each transistor Q5 and Q of the word driver unit 11
When both the signal lines connected to the bases of the word line WL+ become low level, the word decoder unit 11 outputs a high level word line selection signal and applies it to the high voltage side word line WL+.

In this way, the word line is selected, and at the same time, the bit decoder 18 applies a high level bit line selection signal to the bit driver 19 connected to the bit line corresponding to the bit address row 800. As a result, each transistor Q22. Q23 and Q24 are turned on. When reading data, the selected memory cell MC
The potentials of bit lines BL and BLB are transmitted to comparison transistors Q25 and Q26 in accordance with the stored data, and output as read data Dout via sense amplifier 20.

Further, when writing data, transistors Q27 and Q28 are turned on or off depending on write data Din, and bit lines F31. Then, data is written into the selected memory cell MC by forcing the potential of BLB to a high or low level.

The above operation is performed when the word address W-ADD does not match the address of the defective circuit part, and therefore when the redundant circuit selection signal SR is at a high level. When the address matches the address of the circuit portion, the output of the comparison gate circuit unit 13, that is, the redundant circuit selection signal SR becomes low level by an operation described later. As shown in FIG. 3, the selection signal SR is at its high level potential H2.
is the intermediate level of the logic signal applied to the input of the word driver unit 11, that is, the base of the transistor Q5 or Q6, and the low level potential L2 of the selection signal SR
The potential is set to a lower level than the low level potential L1 of the logic signal applied to the input of the word driver unit 11. Therefore, the word address W-ADD
indicates a defective circuit part, the selection signal SR
becomes the lowest level L2, the transistor Q7 of the word driver unit 11 is cut off, and the transistor Q
5 or Q6 is turned on, and the potential of the high voltage side word line WL+ becomes a non-selection level. At this time, in the redundant word driver 16, the transistor Q19 is turned off and the transistor Q20 is turned on, so the redundant word v
AWL(R) becomes high level and the redundant memory cell array 7 is selected. If word address W-ADD is P
If the address does not match the address of the defective circuit portion stored in the ROM, the selection signal SR goes to the high level H2, so the output of the redundant word decoder 16 goes to the low level and the redundant memory cell array 7 becomes non-selected. Note that the reference voltage VRF4 applied to the base of the transistor Q20 has a value intermediate between the high level potential H2 and the low level potential L2 of the selection signal SR. Further, at this time, the base potential H2 of the transistor Q7 of the word driver unit 11 becomes an intermediate value (H2) between the high level potential and the low level potential of the input logic signal of the word driver unit +-11. performs the word line selection or non-selection operation as described above depending on the state of the connected decoder line.

The comparison gate circuit (UNISO) 13 is an exclusive OR (EOR)
) circuit, and when the input word address signal and the defective address signal from FROM are both high level or both low level, it outputs the aforementioned low level L2 selection signal SR, and these input address signals If one is high level and the other is low level, the above-mentioned high level H2
A selection signal SR is output. To explain in more detail, when the word address signal is at a high level, the transistor Q1
3 is turned on, transistor Q14 is turned off, and the base potential of output transistor Q18 becomes low level. At this time, if the defective word address signal input from the FROM to the base of the transistor Q16 is at a high level, the transistor Q16 is turned on and the transistor Q15 is turned off, so the base potential of the output transistor Q17 is also at a low level and the selection signal SR is low. level. When the word address signal is at a high level and the defective word address signal is at a low level, the transistor Q16 is turned off and the transistor Q15 is turned on, so that the base potential of the output transistor Q18 is at a low level, but the base potential of the output transistor Q17 is
The base potential of is at a high level. Therefore, the selection signal SR becomes high level H2. When the word address signal is at a low level, transistor Q13 is turned off, transistor Q14 is turned on, and output transistor Q17 is turned off.
base is at a low level. At this time, if the defective word address signal is at a low level, the transistor Q16 is turned off, the transistor Q15 is turned on, and the base of the output transistor Q18 is also at a low level, so that the selection signal SR is at a low level.

When the word address signal is low level and the defective word address signal is high level, the output transistor, transistor Q
Although the base of 17 is at a low level, the output transistor Q1
Since the base of 8 becomes high level, the selection signal SR becomes high level. That is, comparison gate 7 gate circuit unit 1
3 performs an exclusive OR operation of the word address signal and the defective word address signal. Note that the resistor R4 is provided to shift the logic level of the selection signal SR as shown in FIG.

Note that although the above description has been made regarding a redundant circuit for word lines, redundancy switching can also be performed for via lines using a similar circuit.

(Effects of the Invention) As described above, according to the present invention, since the input address is directly input to the comparison gate circuit without going through an address buffer circuit or the like, the delay time of the redundant circuit selection signal can be increased by a simple circuit configuration. It becomes possible to make it extremely short,
For example, even in a high-speed circuit device such as a bipolar memory device, it becomes possible to operate the defective circuit portion by replacing the defective circuit portion with a redundant circuit portion, thereby improving the product yield of semiconductor memory devices and the like.

[Brief explanation of drawings]

1 is a block circuit diagram showing an outline of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block circuit diagram showing details of the device in FIG. 1, and FIG. 3 is a block circuit diagram showing the details of the device in FIG. 2. FIG. 4 is a waveform diagram showing signals of each part, and a block circuit diagram showing an outline of a conventional semiconductor memory device. DESCRIPTION OF SYMBOLS 1... Memory cell array, 2... Word address buffer, 3... Word driver, 4... Bit address buffer, 5... Bit driver, 6... Input/output circuit, 7... Redundancy Memory cell array, 8... Redundant word driver, 9... Programmable read-only memory, lO...
- Comparison gate circuit, 11... Word driver unit, 12... Address buffer unit, 13... Comparison gate circuit unit, 14... Word decoder, 15... Decoder line, 16... Redundant word Driver unit, 17...Bit address buffer, 1B...Bit address decoder, 19-...Bit driver, 20...Sense amplifier, 21...Chip select buffer, 22...Read/write control circuit and write amplifier, Q
l, Q2. -..., Q28...transistor, R1,
R1, -=, R7...Resistance, mouth 1.02. D3...diode, 151, IS2. -・1514... Constant current circuit.

Claims (1)

[Claims] A memory cell array, a redundant memory cell array, a read-only memory that stores the address of the defective circuit portion, and input address data are directly applied and the address of the defective circuit portion is specified by comparing the input address and the address stored in the read-only memory. 1. A semiconductor memory device comprising a comparison circuit that outputs a switching signal for accessing a redundant circuit section in place of a defective circuit section when a defective circuit section is accessed.