JPH0419640B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that has a redundant circuit section to be used in place of a defective circuit section such as a defective memory cell, and that has an input address. The present invention relates to a semiconductor memory device that switches between a defective circuit portion and a redundant circuit portion by directly comparing the address of the defective circuit portion.

(Prior Art) FIG. 4 schematically shows a conventional random access memory device. The memory device in the figure has a word line
A memory cell array 1 having memory cells connected to WL and bit line BL, respectively, an address buffer 2 for word addresses, a word driver 3, an address buffer 4 for bit addresses, a bit driver 5, a sense amplifier and a write amplifier. The input/output circuit 6 is equipped with an input/output circuit 6.

In the memory device of FIG. 4, when the write enable signal WE is at a high level, for example, the write mode is entered, and the memory cell corresponding to the word address W-ADD and bit address B-ADD is selected, and data is transferred to the memory cell. is written. That is, the word address W-ADD is input to a decoder (not shown) via the address buffer 2, and a word line selection signal is generated. Then, the word driver 3 drives the selected word line based on this word line selection signal. Similarly, bit address B-ADD is input to a decoder (not shown) via address buffer 4. Then, the bit line selection signal generated by the decoder is input to the bit driver 5 to drive the selected bit line. The word line selected in this way
Data is written to WL and bit line BL by inputting write data Din via the write amplifier in the input/output circuit 6. In the case of data reading, the write enable signal WE is set to a low level, for example, and the word address W-ADD and bit address B-ADD are set as in the case of writing.
Word line WL and bit line BL are selected by ADD. The word line selected in this way
Information in the memory cells connected to WL and bit line BL is amplified by a sense amplifier in input/output circuit 6 and output as read data Dout.

(Problems to be Solved by the Invention) In the conventional memory device as described above,
In particular, in the case of high-speed memory devices such as bipolar memory devices, redundant memory cells and the like are not provided. Therefore, if, for example, a certain memory cell in the memory cell array 1 or a word driver unit connected to a certain word line is defective, the memory device itself becomes a defective product, making it impossible to increase the manufacturing yield of semiconductor memory devices. There was this inconvenience.

The present invention was created in view of the problems with the conventional type described above, and allows switching between a defective circuit portion and a redundant circuit portion without causing operational delays or an increase in area due to the adoption of a redundant memory configuration. It is an object of the present invention to provide a semiconductor memory device which can perform the process at high speed, and can provide a redundant circuit part even in a high-speed memory device such as a bipolar memory device, and which can increase manufacturing yield. The purpose is

In order to solve the above problems, a semiconductor memory device according to the present invention has a plurality of memory cells and a plurality of word lines,
It has a memory cell array in which each of the memory cells is constituted by an ECL type flip-flop, a plurality of memory cells and a plurality of redundant word lines, and each of the memory cells is constituted by an ECL type flip-flop. first means having a redundant memory cell array and a first group of ECL gate circuits responsive to an address signal, each ECL gate circuit having a base and an emitter for receiving one bit of the address signal; a first transistor having an emitter coupled to an emitter of the first transistor; and a first amplifier for receiving and amplifying an output signal from the first group of ECL gate circuits. first means comprising: a group of transistor circuits for use in a circuit; and a second means operably connected to the first means;
A second means having an ECL gate circuit group,
Each ECL gate circuit includes a plurality of third transistors connected to receive the output signal from the first group of amplifying transistor circuits and having an emitter, and an emitter coupled to each emitter of the third transistor. a fourth transistor connected to the word line and having the second ECL
a driving transistor that drives the word line in response to an output signal from the gate circuit group and selects a memory cell in the memory cell array in response to the address signal from the first means. second means for storing at least one defective memory address signal of at least one defective memory cell in the memory cell array; and third means operably connected to the third means. , the third
A fourth means having an ECL gate circuit group,
Each ECL gate circuit includes a fifth transistor having a base connected to receive the address signal, and a sixth transistor for receiving the bad memory address signal and comparing the bad memory address signal with the address signal. transistors connected to said fifth and sixth transistors, respectively, having emitters connected at a common node and having bases for receiving output signals from said fifth and sixth transistors, respectively. a second amplification transistor circuit group having two amplification transistors for amplifying the output signal;
receiving the address signal independently of the third means, receiving at least one defective memory address signal from the third means, and comparing the address signal with the defective memory address signal. a fourth means; operably connected to the fourth means;
A fifth means having an ECL gate circuit group,
a seventh transistor in which each ECL gate circuit has a base and an emitter connected to the node of the two amplification transistors in the second amplification transistor circuit group to receive a signal from the node; an eighth transistor having an emitter coupled to an emitter of the seventh transistor; and an eighth transistor connected to the redundant word line and configured to output a respective redundant word in response to an output signal from the fourth group of ECL gate circuits. a redundant driving transistor for driving a line and selecting one of the memory cells in the redundant memory cell array corresponding to one of the defective memory cells in the memory cell array; The memory cell selection means in the second means is operably connected to the nodes of the two amplifying transistors, and is activated when the address signal is inconsistent with the defective memory address signal. The memory cell selection means in the fifth means is activated when the address signal matches the defective memory address signal.

(Function) By using the above-mentioned means, the input address and the address of the defective circuit part stored in the read-only memory are directly compared, so that a switching signal for accessing the redundant circuit part, that is, redundant circuit selection is generated. It becomes possible to extremely reduce signal delay time, and selection of redundant circuits can be performed without affecting access time etc. even in high-speed memory devices such as bipolar memory devices.

In addition, each component for normal memory access and redundancy is configured with ECL gates, and a switching signal that prohibits access to normal memory cells when a defective memory address is detected is sent to the last word driver.
Since it is added to the reference signal input side of the ECL gate,
It is possible to determine whether or not to select a redundant cell independently of and in parallel with the normal decoding operation, and by adopting a redundant memory configuration, it is possible to determine whether or not to select a redundant cell. There is no need to add any elements, and therefore there is no operational delay or area increase due to the adoption of a redundant memory configuration.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 1 schematically shows a semiconductor memory device according to an embodiment of the present invention. As an example, the memory device shown in the figure is configured to switch between a defective circuit section and a redundant circuit section on a per word line basis, and includes a memory cell array 1, an address buffer 2 for word addresses, and a word driver 3. , a redundant memory cell array 7 connected to a redundant word line, a redundant word driver 8, and a programmable read-only memory (hereinafter simply referred to as
PROM 9), and a comparison gate 10 for comparing the input word address W-ADD with the read data of PROM 9. In addition, in FIG. 1, the bit address address buffer,
Illustrations of bit drivers, input/output circuits, etc. are omitted. Further, a similar configuration is used when switching redundant circuits on a bit line basis.

In the storage device shown in FIG. 1, when a write or read operation is performed, a bit address is applied to an address buffer (not shown) for a bit address, and a word address W-ADD is applied to an address buffer 2 for a word address. is input. In the address buffer 2, the word address W-ADD is amplified to a predetermined level and decoded to generate a word line selection signal, which is input to the word driver 3. At this time, if the redundant circuit selection signal SR is not applied from the comparison gate 10, the word line selection signal is applied to the word line of the memory cell array 1 and a predetermined word line is selected. A write or read operation is performed in the same manner as the device.

The word address W-ADD is also applied to comparison gate 10 and compared with address data from PROM 9 indicating a defective circuit portion, such as a defective word. As a result of this comparison, if the two addresses do not match, the redundant circuit selection signal SR is not output, but if the two addresses match, the selection signal SR is output and applied to each word driver 3 and 8. The word driver 3 is inhibited when the selection signal SR is applied, and the word line selection signal for the memory cell array 1 is cut off. On the contrary,
The redundant word driver 8 inputs a word line selection signal to the redundant memory cell array 7 by applying the selection signal SR. As a result, the redundant memory cell array 7
is selected and data is written to or read from the memory cell array 7. In addition,
The signal path indicated by the dotted line in Figure 1 is
This is for writing the address of the defective circuit part into PROM9. That is, when a defective memory cell is detected by an operation test in a wafer state, for example, the address W-ADD of the word containing the defective memory cell is written into the PROM 9 in response to application of the write signal WT.

FIG. 2 shows a detailed configuration of the storage device shown in FIG. 1. In FIG. 2, the memory cell array 1 includes a plurality of memory cells MC connected between a high voltage side word line WL+, a low voltage side word line WL-, and bit lines BL and BLB. Memory cell MC is
For example, PNP type transistors Q1, Q2 and
NPN multi-emitter transistor Q3, Q4
It is a flip-flop type. In addition, the low voltage side word line WL− and the low voltage side power supply terminal Vee
A constant current circuit IS1 is connected between them. Each high voltage side word line WL+ is connected to a constant current circuit with transistors Q5, Q6, Q7 whose emitters are commonly connected.
IS2, load resistor R1, and driver transistor Q8
A word driver unit 11 having the following is connected. An address buffer unit 12 and a comparison gate unit 13 are provided for each bit of word address W-ADD. The address buffer unit 12 includes an input emitter follower having a transistor Q8, a diode D1, and a constant current circuit IS3, and transistors Q9 and Q1.
0, a current switch circuit including a constant current circuit IS4, load resistors R2 and R3, and a diode D2. The output of address buffer unit 12 is connected to word decoder 14. The word decoder 14 is inserted between a decoder line 15 consisting of a plurality of signal lines, a plurality of constant current sources IS15 connected to each signal line, and each output of the address buffer unit 12 and the decoder line 15. A multi-emitter transistor Q11 is provided. In addition, in FIG. 2, only one of the outputs of the address buffer unit 12, that is, the multi-emitter transistor Q11 connected to the collector of the transistor Q10, is shown, but in reality, the collector of the transistor Q9 and the decoder are connected. line 1
Transistors corresponding to the transistor Q11 are also provided between the address buffer unit of the other bits and the decoder line 15, respectively. The emitter of each of these multi-emitter transistors is connected to each signal line of the decoder line 15 as appropriate. Further, the bases of the transistors Q5 and Q6 of the word driver unit 11 are also connected to the signal line of the decoder line 15, respectively.

The comparison gate circuit unit 13 is provided corresponding to each bit of the word address W-ADD, and includes transistors Q12, Q13,..., Q18, constant current circuits IS5, IS6, IS7, IS8, diodes D3,
It is composed of resistors R4, R5, R6, etc. The outputs of the comparison gate units corresponding to each bit are connected together and connected to the base of the transistor Q7 of the word driver unit 11 described above and the input of the redundant word driver described later, and are connected to the redundant circuit selection signal SR.
supply.

The redundant word driver 16 includes transistors Q19 and Q20 that constitute an operating circuit, a constant current circuit IS9,
It includes a load resistor R7 and a driver transistor Q21. The output or emitter of driver transistor Q21 is connected to high voltage side word line WL(R)+ of redundant memory cell array 7. A memory cell MC is connected between the high voltage side word line WL (R) + and the low voltage side word line WL (R) -, and the low voltage side word line WL (R) - has a constant current for current discharge. A circuit IS10 is connected. Note that each bit line is provided in common to the memory cell array 1 and the redundant memory cell array 7.

In FIG. 2, 17 is an address buffer for bit addresses, 18 is a bit address decoder, and 19 is a bit driver, which includes multi-emitter transistors Q22, Q23, transistor Q24, and constant current circuits IS12, IS13, IS.
14. Further, 20 is a sense amplifier, which includes transistors Q25 and Q2.
6 to each bit line BL and BLB. Reference numeral 21 is a chip select buffer that activates each circuit in response to a chip select signal CS. Reference numeral 22 denotes a read/write control circuit and a write amplifier, which drive each bit line BL and BLB via transistors Q27 and Q28.

In the semiconductor memory device having the above structure, when writing and reading operations are performed, the word address W-ADD and the bit address B-ADD are applied, and the chip select signal CS is set to a high level, for example. Further, the write enable signal WE is set to a high level and a low level, respectively, in accordance with write and read operations. Depending on the level of each bit of word address W-ADD, a high level or low level signal is applied from each address buffer 12 to each signal line of decoder line 15 via multi-emitter transistor Q11 and the like. Each signal line of the decoder line 15 is connected to a plurality of multi-emitter transistors, and if at least one of the outputs of these multi-emitter transistors is at a high level, the signal line also becomes at a high level. Then, each transistor Q5 and Q of the word driver unit 11
When the signal lines connected to the bases of 6 become low level, the word decoder unit 11 outputs a high level word line selection signal and selects the high voltage side word line.
Apply to WL+. In this way, the word line is selected, and a high level bit line selection signal is applied by the bit decoder 18 to the bit driver 19 connected to the bit line corresponding to bit address B-ADD. This turns on each transistor Q22, Q23, and Q24.
When reading data, the potentials of bit lines BL and BLB are transmitted to comparison transistors Q25 and Q26 in accordance with the data stored in the selected memory cell MC, and are outputted as read data Dout via the access amplifier 20. Also, when writing data, write data Din
Accordingly, transistors Q27 and Q28 are turned on or off, and the potentials of bit lines BL and BLB are forcibly set to high or low level to write data into the selected memory cell MC.

The above operation is performed when the word address W-ADD does not match the address of the defective circuit part, and therefore when the redundant circuit selection signal SR is at a high level.
If it matches the address of the defective circuit part input from the PROM, the comparison gate circuit unit 1
The output of No. 3, that is, the redundant circuit selection signal SR becomes low level by the operation described below. As shown in FIG. 3, the selection signal SR has its high level potential H2 at an intermediate level of the logic signal applied to the input of the word driver unit 11, that is, the base of the transistor Q5 or Q6, and The low level potential L2 of the signal SR is set to a lower level than the low level potential L1 of the logic signal applied to the input of the word driver unit 11. Therefore, the word address W-ADD
indicates a defective circuit part, the selection signal SR becomes the lowest level L2, the transistor Q7 of the word driver unit 11 is cut off, the transistor Q5 or Q6 is turned on, and the potential of the high voltage side word line WL+ increases. It becomes a non-selection level. At this time, in the redundant word driver 16, the transistor Q19 is cut off and the transistor Q20 is turned on, so that the redundant word line WL
(R)+ becomes high level and redundant memory cell array 7
is selected. If the word address W-ADD
If the address does not match the address of the defective circuit portion stored in the PROM, the selection signal SR goes to the high level H2, so the output of the redundant word driver unit 16 goes to the low level and the redundant memory cell array 7 becomes non-selected. Note that the transistor Q20
The reference voltage VRF4 applied to the base of is the high level potential H2 and low level potential L of the selection signal SR.
It is assumed to be a value between 2 and 2. At this time, the base potential H2 of the transistor Q7 of the word driver unit 11 becomes an intermediate value (H2) between the high level potential and the low level potential of the input logic signal of the word driver unit 11, so the word driver unit 11 is connected. The word line selection or non-selection operation as described above is performed depending on the state of the decoder line.

The comparison gate circuit unit 13 constitutes an exclusive OR (EOR) circuit, and when the input word address signal and the defective address signal from the PROM are both high level or both low level, the above-mentioned low level L2 is set. When one of these input address signals is at a high level and the other is at a low level, the above-mentioned selection signal SR at a high level H2 is output. To explain in more detail, when the word address signal is at high level, transistor Q13 is turned on, transistor Q14 is turned off, and the base potential of output transistor Q18 becomes low level. At this time, if the defective word address signal input from the PROM to the base of transistor Q16 is at a high level, transistor Q16 is turned on and transistor Q15 is turned off, so the base potential of output transistor Q17 is also at a low level and the selection signal SR is low. level. When the word address signal is high level and the defective word address signal is low level, transistor Q16
is off and transistor Q15 is on, so the base potential of output transistor Q18 is at a low level, but the base potential of output transistor Q17 is at high level. Therefore, the selection signal SR
becomes a high level H2. When the word address signal is at a low level, transistor Q13 is turned off, transistor Q14 is turned on, and the base of output transistor Q17 becomes low level. At this time,
If the defective word address signal is at a low level, the transistor Q16 is turned off, the transistor Q15 is turned on, and the base of the output transistor Q18 is also at a low level, so that the selection signal SR is at a low level.
When the word address signal is at a low level and the defective word address signal is at a high level, the base of the output transistor Q17 is at a low level, but the base of the output transistor Q18 is at a high level, so the selection signal SR is at a high level. Become. That is, the comparison gate circuit unit 13 performs an exclusive OR operation on the word address signal and the defective word address signal. Note that the resistor R4 is provided to shift the logic level of the selection signal SR as shown in FIG.

Note that although the redundancy circuit for word lines has been described above, redundancy switching can also be performed for bit lines using a similar circuit.

(Effects of the Invention) As described above, according to the present invention, since the input address is directly input to the comparison gate circuit without going through an address buffer circuit or the like, the delay time of the redundant circuit selection signal can be reduced by a simple circuit configuration. This makes it possible to operate by replacing defective circuit parts with redundant circuit parts even in high-speed circuit devices such as bipolar memory devices, improving product yields of semiconductor memory devices and other devices. be done.

Also, each component for memory access is
It consists of ECL gates, and a switching signal that prohibits normal memory access during redundancy is applied to the reference signal input side of the last ECL gate of the word driver, so redundant cell selection operation can be performed in parallel with normal decoding operation. In addition, it is possible to prevent operational delays and area increases due to the adoption of a redundant memory configuration.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram schematically showing a semiconductor memory device according to an embodiment of the present invention, and FIG.
A block circuit diagram showing details of the device shown in the figure; FIG. 3 is a waveform diagram showing signals of each part in the device shown in FIG. 2;
FIG. 4 is a block circuit diagram schematically showing a conventional semiconductor memory device. 1... Memory cell array, 2... Word address buffer, 3... Word driver, 4... Bit address buffer, 5... Bit driver, 6
...Input/output circuit, 7...Redundant memory cell array,
8... Redundant word driver, 9... Programmable read only memory, 10... Comparison gate circuit, 11... Word driver unit, 12...
Address buffer unit, 13... Comparison gate circuit unit, 14... Word decoder, 15...
...Decoder line, 16...Redundant word driver unit, 17...Bit address buffer, 18...
... Bit address decoder, 19 ... Bit driver, 20 ... Sense amplifier, 21 ... Chip select buffer, 22 ... Read/write control circuit and write amplifier, Q1, Q2, ..., Q28 ...
Transistor, R1, R1,..., R7...Resistor,
D1, D2, D3...Diode, IS1, IS2,
...IS14... Constant current circuit.

Claims (1)

[Claims] 1. It has a plurality of memory cells (MC) and a plurality of word lines WL+, WL-, and each of the memory cells has a
It has a memory cell array 1 composed of ECL type flip-flops ( _Q1 to _Q4 ), a plurality of memory cells (MC) and a plurality of redundant word lines WL(R)+, WL(R)-, A redundant memory cell array 7 in which each of the memory cells is constituted by an ECL type flip-flop;
First means 12 comprising a group of ECL gate circuits, each ECL gate circuit comprising a first transistor having a base and an emitter for receiving one bit of said address signal.
Q ₉ ; a second transistor Q ₁₀ having an emitter coupled to the emitter of the first transistor; and a first amplifying transistor for receiving and amplifying the output signal from the first group of ECL gate circuits. a first means 12 comprising: a transistor circuit group Q ₁₁ ; and a second means operably connected to the first means;
Second means 11 having a group of ECL gate circuits, each ECL gate circuit comprising a plurality of third transistors connected to receive the output signal from the first group of amplifying transistor circuits and having an emitter. Q ₅ , Q ₆ , and a fourth transistor Q ₇ having an emitter coupled to each emitter of the third transistor, connected to the word line and connected to the output signal from the second ECL gate circuit group. a driving transistor Q ₈ responsively driving the word line and selecting a memory cell in the memory cell array in response to the address signal from the first means; and a third means 9 for storing at least one defective memory address signal of at least one defective memory cell in said memory cell array; and third means 9 operatively connected to said third means;
Fourth means 13 comprising a group of ECL gate circuits, each ECL gate circuit comprising: a fifth transistor Q 13 having a base connected to receive said address signal; and a fifth transistor Q ₁₃ receiving said bad memory address signal. , a sixth transistor _Q16 for comparing the address signal and the defective memory address signal, each connected to the fifth and sixth transistors and having emitters connected at a common node and connected to the fifth and sixth transistors respectively; and two amplifying transistors Q ₁₇ each having a base for receiving an output signal from the sixth transistor and amplifying the output signal.
a second amplifying transistor circuit group having Q ₁₈ , which receives the address signal independently of the first means, and receives at least one of the address signals from the third means;
a fourth means 13 operatively connected to the fourth means and comprising: receiving a number of bad memory address signals and comparing the address signal with the bad memory address signal; of
A fifth means 16 having an ECL gate circuit group, wherein each ECL gate circuit is connected to the node of the two amplification transistors in the second amplification transistor circuit group to receive a signal from the node. a seventh transistor having a base and an emitter for receiving
Q ₁₉ , an eighth transistor Q ₂₀ having an emitter coupled to an emitter of the seventh transistor;
Driving each redundant word line in response to an output signal from the ECL gate circuit group to select one of the memory cells in the redundant memory cell array corresponding to one of the defective memory cells in the memory cell array. Redundant drive transistor Q ₂₁
and a fifth means 16 comprising: The memory cell selection means in the second means 11 includes the two amplification transistors Q ₁₇ and Q ₁₈ .
The memory cell selecting means in the fifth means 16 is operably connected to the node of the memory cell selection means in the fifth means 16, and is activated when the address signal is inconsistent with the defective memory address signal. A semiconductor memory device characterized in that it is energized when a match occurs.