JPS61120400A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To switch a defective circuit part and a redundancy circuit part through simple circuit constitution by providing a redundancy address decision circuit and a redundancy circuit selection part, and placing a decoder line in an unselected state on the basis of a redundancy circuit selection signal. CONSTITUTION:A selection signal SR is outputted from a comparing gate circuit 13 when a word address ADD coincides with a defective word address inputted from a programmable read-only memory PROM 12 stored with the address of the redundancy circuit part. Then, all signal lines of a decoder line are held at a high level with said selection signal SR and placed in the unselected state to intercept a word line selection signal to be applied to a memory cell array 1. On the other hand, a redundancy word driver 11 inputs a word line selection signal to a redundancy memory cell array 10 when applied with the selection signal SR. Consequently, the redundancy memory cell array 10is selected to write or read data in or out of the memory cell array 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device and a semiconductor memory device.
The present invention relates to a semiconductor memory device which has a redundant circuit part which can be used in place of a defective circuit part such as a redundant circuit part, such as a redundant circuit part, and which is switched between the defective circuit part and the redundant circuit part by controlling the potential of a decoder line.

(Prior Art) FIG. 3 partially shows a bipolar memory device as a conventional semiconductor memory device. The memory device shown in the figure includes a memory cell array 1, a word driver 2, a word decoder 3, and an address buffer 4 for word addresses. The memory cell array l has a high voltage side word line WL+
A plurality of memory cells MC are connected between the word line WL- on the low voltage side and the bit lines BL and BLB. Each memory cell MC is of a well-known flip-flop type. The word driver 2 includes a plurality of word driver units 2a each corresponding to a word line.

2b-. Each word driver unit has the same configuration, for example, the word driver unit 2a has transistors Ql and Q2 whose emitters are commonly connected, and a transistor Ql and Q2 whose emitters are connected in common, and which are connected between the commonly connected emitters of these transistors and the low voltage side power supply terminal Vee. Constant current circuit ISi includes a load resistor R1 connected between the collector of the transistor Q1 and the high voltage side power supply terminal Vcc, and a driver transistor Q3 whose base is connected to the collector of the transistor Q1. The address buffer 4 has a plurality of address buffer units, and one address buffer unit 4a.
are transistors Q7. whose emitters are commonly connected. Q8
, a constant current circuit IS3, load resistors R3 and R4, a transistor Q9 and a constant current circuit 134 forming an incoming limiter follower circuit, and a transistor QIO and a constant current circuit IS5 forming an emitter follower circuit for applying a reference voltage. The word decoder 3 also includes a multi-emitter transistor Ql that receives the output of the address buffer unit 4a.
1, Q12, and an address line 5 having a plurality of signal lines to which the emitters of these multi-emitter transistors are connected, and a constant current source connected between each signal line of the address line 5 and the low voltage side power supply terminal V2O. circuit 156
, 157. Equipped with IS8 and IS9. A unit corresponding to the address buffer unit 4a is provided for each bit of the word address, and its output is appropriately connected to each signal line of the decoder line 5 via two multi-emitter transistors. Further, each of the decoder lines 5 is connected to the input of each word driver unit 2a, 2b, -1.

In the memory device of FIG. 3, when writing and reading operations are performed, a word address ADD is applied to the word address buffer 4, and a bit address is applied to a bit address buffer (not shown). Depending on the level of each bit of word address ADD, a high level or low level signal is applied from each address buffer unit 4a etc. to each signal line of decoder line 5 via multi-emitter transistors Qll, Q12 etc.

Each signal line of the decoder line 5 is connected to a plurality of multi-emitter transistors, and if at least one of the outputs of these multi-emitter transistors is at a high level, the potential of the signal line becomes a high level. Then, when the signal line connected to the base of the input transistor Ql of the word driver unit, for example 2a, becomes low level, the word driver unit, for example, the word driver.

The driver unit 2a outputs a high level word line selection signal and applies it to the high voltage side word line WL+.

In this way, a word line is selected, and a pair of bit lines BL and B are selected by a bit decoder (not shown) or the like.
LB is selected. Data is written to or read from memory cells MC connected to the word line and bit line pair selected in this manner.

However, in the conventional memory devices as described above, especially in the case of high-speed memory devices such as bipolar memory devices, redundant memory cells and the like are not provided.

Therefore, for example, if a certain memory cell in the memory cell array 1 or a word driver unit connected to a certain word line is defective, the memory device itself becomes defective, making it difficult to increase the manufacturing yield of semiconductor memory devices. The problem was that I couldn't do it.

(Problems to be Solved by the Invention) In view of the problems with the conventional type described above, the present invention provides a semiconductor memory device in which switching between a defective circuit portion and a redundant circuit portion is performed using an extremely simple circuit configuration. , and aims to improve the manufacturing yield of memory devices.

(Means for Solving the Problems) The semiconductor memory device according to the present invention includes a decoder line to which address buffer circuit outputs are appropriately connected, and a driver gate circuit whose input is connected to the decoder line and drives word lines, etc. and a redundant address determination circuit that determines whether the input address matches the address of the defective circuit portion and outputs a redundant circuit selection signal, and a redundant circuit selection section, the redundant circuit selection section being The decoder line is set to a non-selected state based on the redundant circuit selection signal.

(Function) By using the above-mentioned means, when the redundant circuit selection signal is output from the redundant address determination circuit, the decoder line is brought into a non-selected state (for example, at a high potential level)2.

As a result, the drive signal output from the driver gate circuit becomes a non-selection level, the memory cell array including the defective circuit portion becomes non-selected, and the redundant circuit portion is selected.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a semiconductor memory device according to an embodiment of the present invention. The storage device shown in the figure is configured to switch between a defective circuit section and a redundant circuit section in units of word lines, for example, and includes a memory cell array l, a word driver 2, an address buffer 4 for word addresses, and a decoder. In addition to the line 5, there is a redundant memory cell array IO1 connected to the redundant word line, a redundant word driver 11, a programmable read-only memory (hereinafter simply referred to as FROM) 12 that stores the address of the redundant circuit part, and an input word address ADD. A comparison gate 13 for comparing read data from the PROM 12 is provided.

Note that, in FIG. 1, illustrations of a bit address address buffer, a bit driver, an input/output circuit, etc. are omitted.

In the memory device shown in FIG. 1, write and read operations are performed by applying a word address ADD and a bit address to an address buffer (not shown) for bit addresses, similarly to the circuit shown in FIG. At this time, word address ADD is applied to comparison gate 13 and PRO
It is compared with address data indicating a defective circuit portion, such as a defective word, from M12. As a result of this comparison, if both addresses do not fail, the redundant circuit selection signal (hereinafter simply referred to as selection signal) SR is not output, and the word driver 2 operates the memory cell array by the same means as in the case of FIG. 1 is accessed and data reading or data writing is performed.

On the other hand, when the word address ADD and the defective word address input from the PROM 12 match, the comparison gate circuit 13 outputs the selection signal SR. This selection signal SR sets all the signal lines of the decoder line 5 to a high level non-selected state, and the word line selection signal to be applied to the memory cell array I is cut off.

On the other hand, the redundant word driver 11 inputs a word line selection signal to the redundant memory cell array IO by applying the selection signal SR. As a result, the redundant memory cell array 10 is selected, and data is written to or read from the memory cell array 10.

FIG. 2 shows a detailed circuit configuration of the storage device shown in FIG. 1.

The circuit shown in FIG. 3 includes a redundant memory cell array 10, a redundant word driver 11, and a comparison gate circuit 1 in addition to the circuit shown in FIG.
3. Diode D2 forming the AND gate. D3.・
-., Dn, resistor R7, and multi-emitter transistor Q23 are added. A selection signal SR is applied to the base of the multi-emitter transistor Q23, and each emitter is connected to the base of the transistor Q20 through each signal line of the decoder line 5 and the redundant word driver 11, respectively. Other parts are 3rd
It has the same configuration as the circuit shown in the figure.

The redundant memory cell array IO has a high voltage side word line WL (
It has a memory cell MC connected between R) + and a low voltage side word line WL (R)- and between memory cell array 1 and a common bit line pair BL, BLB. Redundant word driver 11 has the same configuration as each word driver unit of word driver 2, and includes transistors Q20 . Q21
．． Q22, resistor R8, and constant current circuit 1514. Note that the transistor Q2. is connected to the base of the transistor Q21. Similarly to Q5, reference voltage VRFI is applied.

Comparison gate circuits 13 are provided corresponding to each bit of word address ADD, one of which is connected to transistors Q13. Q14. ..., Q19, constant current circuit l5I
O,rsll, 1312. l513, diode DI,
It is composed of resistors R6, R7, etc. transistor Q
13, the diode Di and the constant current circuit 15IO constitute an input limiter follower circuit. Transistor Q14.
The emitters of Q15 are commonly connected and connected to the low voltage side power supply terminal Vee via a constant current circuit 1511. Transistor Q16. The emitters of Q17 are also commonly connected and connected to the low voltage side power supply terminal Vee via a constant current circuit 1512. Note that reference voltages VRF3 and VRF4 are applied to the bases of transistors Q15 and Q16, respectively, and the output of a FROM (not shown) for storing defective addresses is applied to the base of transistor Q17.

Transistor Q15. The collectors of Q16 are both connected to the base of transistor Q19, and the collectors of transistors Q14 and Q17 are both connected to the base of transistor QI8. Transistors Q18°Q19 and constant current circuit 1513 constitute a logical sum (OR) circuit.

The operation of the semiconductor memory device having the above configuration will be explained. Comparison gate circuit 13, exclusive NOR (ENOR)
The input word address signal A constitutes the circuit.
When the defective address signals from DD and FROM are both high and low, a high-level selection signal SR is output, and when one of these input signals is high and the other is low, a low-level selection signal is output. Output SR. To explain in more detail, when the word address signal ADD is at a high level, the transistor Q14 is turned on, the transistor Q15 is turned off, and the base potential of the output transistor Q1B becomes a low level. At this time, Pl? From OM to transistor Ql? If the defective word address signal input to the base of is at a high level, transistor Q17 is turned on.
Since the transistor Q16 is turned off, the base potential of the output transistor Q19 becomes high level, and the selection signal SR becomes high level.

When the word address signal ADD is at high level and the defective word address signal is at low level, transistor Q
Since the transistor Q17 is turned off and the transistor Q16 is turned on, the base potential of the output transistor Q19 is at a low level, and the base potential of the output transistor Q18 is also at a low level as described above.

Therefore, the selection signal SR becomes low level. When the word address signal ADD is at a low level, the transistor Q14 is turned off, the transistor Q15 is turned on, and the base of the output transistor Q19 becomes low level. At this time, if the defective word address signal is at a low level, the transistor Q17 is turned off, the transistor Q16 is turned on, and the base of the output transistor Q18 is at a high level, so that the selection signal SR is at a high level. When the word address signal is at a low level and the defective word address signal is at a high level, the base of the output transistor Q18 is at a low level, and the base of the output transistor Q19 is at a low level, so that the selection signal SR is at a low level. That is, the comparison gate circuit 13 receives the word address signals ADD and F.
Exclusive NOR (ENOR) operation is performed on the defective word address signal input from the ROM.

In the circuit of FIG. 2, if the word address ADD does not match the defective word address, then the selection signal S
When R is at a low level, the output of the redundant word driver II becomes a low level, the high voltage side word line WL (R)+ of the redundant memory cell array 10 becomes a low level, and the redundant memory cell array 10 becomes a non-selected state. . Then, data reading and writing operations as explained in FIG. 3 are performed.

On the other hand, if the word address ADD and the defective word address input from FROM match, all the outputs of the comparison gate circuits 13 corresponding to each bit become high level due to the above operation, and the selection signal SR becomes high level. becomes. This allows multi-emitter transistor Q2
3, the potentials of all signal lines of decoder vA5 become high level, and the potentials of all high voltage side word lines WL+ of memory cell array 1 become low level, that is, non-selection level. At this time, the transistor Q20 is turned on in the redundant word driver 11, and the transistor Q20 is turned on.
21 cant off, the redundant word line WL (R)
1 becomes high level, and the redundant memory cell array IO is selected. In this way, the redundant memory cell array 10 is accessed in place of the defective word in the memory cell array 1. Note that if the word address ADD does not match the defective word address stored in the PROM, the selection signal S
Since R becomes a low level as described above, the output of the redundant word driver 11 becomes low and becomes healthy, so that the redundant memory cell array 10 becomes non-selected.

In the above description, a redundancy circuit for word lines has been described, but it is clear that according to the present invention, redundancy switching can also be performed for bit lines and the like using a similar circuit.

(Effects of the Invention) As described above, according to the present invention, with an extremely simple circuit configuration, redundant circuit switching in a semiconductor memory device can be performed accurately, and product yield can be significantly improved. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram schematically showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block circuit diagram showing details of the device in FIG. 1, and FIG. 3 is a conventional semiconductor memory device. FIG. 2 is a block circuit diagram showing the configuration of the device. 1: Memory cell array, 2: Word driver, 3: Word decoder, 4: Word address bus sofa, 5: Decoder line, 10: Redundant memory cell array, 11: Redundant word driver, 12: Programmable read-only memory, 13: Comparison gate circuit, ui, Q2. -, az3: transistor, R1, R
2,..., R8: resistance, ISI, 152. -,. 1514: Constant current circuit, D
I, D2. -”, Dn: Diode. 4. Patent applicant Fujitsu Limited Patent application agent

Claims (1)

[Claims] Memory cell array, redundant memory cell array, address buffer circuit, decoder line to which the address buffer circuit output is connected as appropriate, driver gate circuit whose input is connected to the decoder line, and whether or not the input address matches the address of the defective circuit portion. and a redundant circuit selection section that selects a redundant memory cell array in place of a defective circuit portion by setting a decoder line to a non-selected state based on a switching signal output from the redundant address determining circuit. A semiconductor memory device characterized by: