JPS61120291U - - Google Patents
Info
- Publication number
- JPS61120291U JPS61120291U JP235885U JP235885U JPS61120291U JP S61120291 U JPS61120291 U JP S61120291U JP 235885 U JP235885 U JP 235885U JP 235885 U JP235885 U JP 235885U JP S61120291 U JPS61120291 U JP S61120291U
- Authority
- JP
- Japan
- Prior art keywords
- terminal voltage
- dividing resistor
- smoothing capacitor
- voltage dividing
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000009499 grossing Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Protection Of Static Devices (AREA)
Description
第１図乃至第３図は本考案のインバータ装置に
係り、第１図は一実施例の回路図、第２図は主要
素子の動作図、第３図は他の実施例の回路図を示
し、第４図は従来のインバータ装置の回路図であ
る。
１…整流回路、２…平滑コンデンサ、３…逆変
換回路、４…負荷、５，７，８，１１…抵抗、６
…ＭＯＳ―ＦＥＴ、９，１３…ダイオード、１０
…ツエナーダイオード、１２…コンデンサ、２０
…トランジスタ、２１…増幅器。
1 to 3 relate to the inverter device of the present invention, in which FIG. 1 shows a circuit diagram of one embodiment, FIG. 2 shows an operation diagram of main elements, and FIG. 3 shows a circuit diagram of another embodiment. , FIG. 4 is a circuit diagram of a conventional inverter device. 1... Rectifier circuit, 2... Smoothing capacitor, 3... Inverse conversion circuit, 4... Load, 5, 7, 8, 11... Resistor, 6
...MOS-FET, 9, 13...Diode, 10
...Zener diode, 12...Capacitor, 20
...Transistor, 21...Amplifier.
Claims (1)
回路の直流出力を平滑コンデンサを介して接続さ
れた逆変換回路により逆変換して負荷を駆動する
インバータ装置において、前記平滑コンデンサに
並列に接続され前記平滑コンデンサの端子電圧を
検出する端子電圧検出手段と、この端子電圧検出
手段の電圧レベル検出を遅延する遅延回路と、前
記平滑コンデンサに直列に接続され前記端子電圧
検出手段からの信号を受けて解除動作する電流抑
制手段とを具備することを特徴とするインバータ
装置。 (2) 端子電圧検出手段は、前記平滑コンデンサ
に並列に接続した分圧抵抗と、この分圧抵抗の負
側に直列に接続したダイオードとこの分圧抵抗の
中間点から負側にツエナーダイオードと抵抗を順
番に接続した直列接続回路とから成り、前記ツエ
ナーダイオードと抵抗との間から電流抑制手段の
制御端子に接続し、制御信号を出力することを特
徴とする実用新案登録請求の範囲第１項記載のイ
ンバータ装置。 (3) 遅延回路は分圧抵抗と、この分圧抵抗の中
間点から負側に接続したコンデンサとダイオード
の直列回路とから成ることを特徴とする実用新案
登録請求の範囲第１項記載のインバータ装置。 (4) 電流抑制手段は、突入電流抑制抵抗と、前
記端子電圧検出手段からの制御信号により開閉制
御される半導体素子とを並列接続して成ることを
特徴とする実用新案登録請求の範囲第１項記載の
インバータ装置。[Claims for Utility Model Registration] (1) An inverter device that drives a load by rectifying an AC power source using a rectifier circuit and inversely converting the DC output of the rectifier circuit using an inverse conversion circuit connected via a smoothing capacitor. , a terminal voltage detection means connected in parallel to the smoothing capacitor for detecting the terminal voltage of the smoothing capacitor; a delay circuit for delaying voltage level detection of the terminal voltage detection means; An inverter device comprising current suppressing means that performs a canceling operation upon receiving a signal from a terminal voltage detecting means. (2) The terminal voltage detection means includes a voltage dividing resistor connected in parallel to the smoothing capacitor, a diode connected in series to the negative side of the voltage dividing resistor, and a Zener diode connected to the negative side from the midpoint of the voltage dividing resistor. A utility model registration claim 1 comprising a series connection circuit in which resistors are connected in order, and is connected to a control terminal of a current suppressing means from between the Zener diode and the resistor to output a control signal. Inverter device described in section. (3) The inverter according to claim 1, wherein the delay circuit comprises a voltage dividing resistor and a series circuit of a capacitor and a diode connected from the midpoint of the voltage dividing resistor to the negative side. Device. (4) The current suppressing means is formed by connecting in parallel an inrush current suppressing resistor and a semiconductor element whose opening/closing is controlled by a control signal from the terminal voltage detecting means. Inverter device described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP235885U JPS61120291U (en) | 1985-01-14 | 1985-01-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP235885U JPS61120291U (en) | 1985-01-14 | 1985-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61120291U true JPS61120291U (en) | 1986-07-29 |
Family
ID=30475960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP235885U Pending JPS61120291U (en) | 1985-01-14 | 1985-01-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61120291U (en) |
-
1985
- 1985-01-14 JP JP235885U patent/JPS61120291U/ja active Pending
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