JPS61115349A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To set the circuit threshold voltage of a CMOS circuit freely by forming potential difference among each substrate and source for a first conduction type channel MOS transistor constituting an input section and a second conduction type channel MOS transistor. CONSTITUTION:A p channel MOS transistor 20 and an n channel MOS transistor 212 form an inverter circuit constituting an input section for a CMOS.IC, and a p channels MOS transistor 22 and an n channel MOS transistor 23 represent transistors organizing circuits after an internal circuit. Voltage VGBP and voltage VGBN are each applied in the reverse bias direction among several source and substrate for the p channel MOS transistor 20 and the n channel MOS transistor 21. Only the threshold voltage of the transistor for the input section is changed by a back-gate-bias effect. Accordingly, circuit threshold voltage can be set freely.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device, particularly to a complementary MO8 integrated circuit device whose circuit threshold voltage can be freely set, and more particularly to a complementary MAMO8 integrated circuit device which can be driven at TTL level. .

[Conventional technology]

FIG. 4 is a circuit diagram showing the minimum unit of the complementary MO8 circuit. In FIG. 4, input terminal 3 receives input signal V+.
The gate of p-channel MOS transistor 1 and the gate of n-channel MOS transistor 2 are commonly connected to
The output terminal 4 that outputs the output signal Vo has a p-channel MO.
The drain 102 of the S transistor and the drain 202 of the n-channel MOS transistor 2 are commonly connected. Further, the substrate and source 101 of p-channel MoS transistor 1 are commonly connected to one voltage power supply terminal Vcc. Further, the source 201 and the substrate of the n-channel MOS transistor 2 are commonly connected to the other power supply terminal Gnd. Figure 5 shows a conventional complementary MO8 semiconductor integrated circuit (under JX, 0MO8/I
FIG. 5, a p-type island region 106 for forming an n-channel MOS transistor is formed in an n-type semiconductor substrate 105, and an insulating layer 107 is formed in a predetermined region on the semiconductor substrate 105. A metal electrode 108 is formed. The p-channel MoS transistor 1 includes a D+ diffusion layer 101 that serves as a source, a D+ diffusion layer 102 that serves as a drain, and a source 101-drain 10 formed on the main surface of a semiconductor substrate 105.
Metal electrode 10 formed on 211 via insulating layer 107
It consists of 8. On the other hand, the n-channel MOS transistor 2 includes an n4 diffusion layer 201 which is formed on the p-type island region 106 and which becomes a source, and an n1 diffusion layer 20 which becomes a drain.
2 and an insulating layer 107 between the source 201 and the drain 202.
and a metal electrode (gate electrode) 108 formed through the gate electrode. Furthermore, n-channel MOS transistor 2
In order to provide a ground potential (3nd) to the source 201 and the p-type island region 106, a p4-type contact layer 1 is formed in the region.
09 is in the region of p-channel MOS transistor 1,
An n+ type contact layer 110 is provided for applying voltage Vcc to source 101 and substrate 105, respectively. FIG. 6 is a diagram showing the input/output voltage and through current characteristics of the conventional 0MO8-IC shown in FIG. 4. In FIG. 6, the horizontal axis represents the input voltage V+ (V) applied to the input terminal 3, and the vertical axis represents the output voltage vo (V) at the output terminal 4 and the p-channel MOS transistor 1.
and the n-channel MOS transistor j2 respectively represent the common current Ice (■A). 6th
In the figure, the solid line is the output voltage Vo with respect to the change in input voltage ■1.
The broken line represents the change in the above-mentioned penetration 11811cG with respect to the change in the input voltage 1. The operation of the conventional 0MO8 IC shown in FIG. 4 will be described below with reference to FIG. When the input voltage V+ is gradually increased from O, the input voltage V
+ is the threshold voltage V of n-channel MOS transistor 2
Until reaching PN, the p-channel MOS transistor 1 is on, the n-channel MOS transistor 2 is off, and the output voltage v0 remains constant at the high level Vcc. Next, with the threshold voltage of p-channel MO8 transistor 1 as Vyr, the input voltage V+ is changed from VTN to Vec.
1Vvrl, MOS transistor 1
and 2 are both turned on, and the output voltage Vo changes from high level to low level. In particular, when the on-resistance values of both MOS transistors 1 and 2 are the same, the output voltage ■. changes rapidly, and at this time the through current ■cc reaches its maximum. The input voltage at this time is the circuit threshold voltage Vye. Next, when the input voltage V+ is between Vcc-IVyrl and Vcc, the p-channel MOS transistor 1 is turned off and the n-channel MOS transistor 2 is turned on.
Output voltage■. is constant at a low level. Usually, MOS transistors 1 and 2 are selected having on-resistance values such that the circuit threshold voltages V and C described above are approximately Vcc/2. The OMO8-IC configured as described above has been widely used in recent years because it has advantages such as low power consumption and a wide operating power supply voltage range. Roughly, with the establishment of silicon gate process, 0 MO
8.ICs are capable of high-speed operation. Therefore, it has become increasingly necessary to use them together with logic circuits including bipolar transistors that also operate at high speed. Figure 7 shows a low-power Schottky transistor logic (hereinafter referred to as
FIG. 2 is a circuit diagram showing the entire inverter circuit (denoted as LSTTL). The inverter circuit shown in FIG. 7 includes a diode-clamped npn bipolar transistor 6.7°8.9;
npn bipolar transistor 10 and resistors 11 and 12
．． 13, 14, 15, 16, an input terminal 17, an output terminal 18, a Schottky barrier diode 5 provided at the next stage of the input terminal 17 in the opposite direction when viewed from the input terminal 17, and a constant voltage power supply terminal ■cc It consists of FIG. 8 is a diagram showing the input/output characteristics of the 18771 circuit shown in FIG. 7. In FIG. 8, the horizontal axis is the input voltage V+ (V) applied to the input terminal 17, and the vertical axis is the output voltage Vo' (v) at the output terminal 18. In FIG. 8, the solid line represents the change in the output voltage Vo' with respect to the change in the input voltage Vt. The operation of the 18771 circuit shown in FIG. 7 will be described below with reference to FIG. The circuit threshold voltage Vr c ' at which the output voltage Vo' changes rapidly in FIG. Input terminal 17
When current flows to the base of the npn transistor 6, the output voltage Vo' becomes high level, and conversely, when the current flows to the base of the npn transistor 6, the output voltage Vo' becomes high level. ' becomes low level. The forward voltage drop of Schottky barrier diode 5 is vs, np
The base-emitter forward voltage of n transistor 6 is Vs
, the base-emitter forward voltage of the npn transistor 8 is Va, the circuit threshold voltage Vrc' of the 18771 circuit shown in FIG. 7 is expressed as Vc' = -Vs +V@ +V6. The power supply voltage VCC of the 18771 circuit is normally 5■
In this case, the voltage Vi is normally 0°4V, and the voltages v1 and vs are both 0.7■. therefore,
From the above equation, the normal circuit threshold voltage VTc' is 1. O
It becomes V. Normally, the high level Vllll of the input voltage of the 18771 circuit is 2 degrees. More than V. -i, vl, yu. , 8wa. □It has been made into an 11th case. [Problems to be solved by the invention] As mentioned above, when 0MO8-IC and bipolar logic circuit are used together, 0MO8-IC also has high level VIN or low level ■ IH input level of bipolar logic circuit. must be able to operate. The above-mentioned 8th
In the case of the 18771 circuit shown in the figure, as already mentioned, the high level VIN of the input voltage is 2 volts, and the low level VIN is 2 volts.
Since IL is 0°8 volts, input voltage v1 is 0.8
It is necessary to set the circuit threshold voltage Vrc of 0MO8-IC in the region between volts and 2 volts. As mentioned above, (in MOS-IC, usually p
By balancing the channel MO8l transistor and the n-channel MOS transistor, the circuit threshold voltage Vyc
is set to 1/2 of the m applied voltage Vcc, but when used together with the L S T T L circuit as described above, the circuit threshold voltage ■Tc is set to 0°8 to 2. The on-resistance value of n-channel MOS transistor 2 is set to be small so that it is between Ov. FIG. 9 shows the circuit threshold voltage VTC obtained by the method described above.
5 is a diagram showing the characteristics of the input/output voltage and through current of the 0MO8 IC shown in FIG. 4 when the voltage is set between O, aV and 2.0 ■. In FIG. 9, point A indicates the input voltage at which a through current begins to flow, which is the threshold voltage VT- of the n-channel MOS transistor 2. In addition, point 8 is the other point where the true current begins to flow, which is the n-channel MO
It is determined by the threshold voltage VTP of the S transistor 1. Normally, these threshold voltages are adjusted to about 0.7V when the power supply voltage Vcc is 5V. in this way,
By adjusting the on-resistance value of the MOS transistors that make up the 0MO8-IC, it is possible to match the circuit threshold voltage of the 0MO8/IG to the circuit threshold voltage of a bipolar logic circuit such as the 18771 circuit that uses a mixed circuit. be. However, in the input/output characteristics of the 0MO8-IC shown in FIG. 9, the low level input voltage VIL shown in FIG.
Or, if we consider the case where a high level input voltage Vl is applied, it is true that the circuit threshold voltage Vrc is set between the low level VIL and the high level VIN, but on the other hand, a very large through current is generated. I can see it flowing. That is, in FIG. 9, point X indicates a through current when a low level input voltage VIL is applied, and point Y indicates a through current when a high level input voltage VIN is applied. In order for the 0MO8-IC to operate at high speed, the n-channel MOS transistor and the on-resistance value of the n-channel MOS transistor must be small, and as a result, the through current, especially at the above-mentioned point Y, reaches several hundreds of amperes.
There was a drawback that low power consumption, which is an advantage of 0MO8 IC, could not be achieved. Moreover, as mentioned above, an n-channel MOS transistor and an n-channel MOS transistor
Providing a difference in on-resistance value between the channel MOS transistor and the channel MOS transistor has the disadvantage that the circuit becomes unbalanced and the circuit configuration becomes difficult. Therefore, the object of this invention is to eliminate the above-mentioned drawbacks and to
When an O3-IC and a bipolar logic circuit are used together, the bipolar logic circuit can sufficiently operate at the standardized input levels of "H" and "L" levels, and has low power consumption and operation. 0MO to maintain high speed
8. Semiconductor integration using IC circuits! It is to provide a 1@ position. Means for Solving Problem E] In the semiconductor integrated circuit according to the present invention, the following means are applied to the first conductivity type channel MOS transistor and the second conductivity type MoS transistor constituting the input stage of the circuit. will be established. That is, an 11th conductivity type semiconductor epitaxial layer is formed on a first conductivity type semiconductor substrate, and a part of the first conductivity type semiconductor epitaxial layer is surrounded by a 211fI type isolation region and a buried layer to form a first conductivity type semiconductor epitaxial layer. Create an island area of type. M of the second conductivity type channel is in this first conductivity type island region.
An OS transistor is formed, and a difference is provided between the potential of the first conductivity type island region and the source potential of the second conductivity type channel MOS transistor. At the same time, an island region of a second conductivity type is formed on the substrate of the first conductivity type, separated from the island region of the second conductivity type, and a channel MOS of the first conductivity type is formed in the island region of the second conductivity type. Form a transistor. Then, a difference is provided between the potential of the second conductivity type island region and the source potential of the first conductivity type channel MO8 transistor. [Operation] Since a potential difference is provided between the substrate and the source of each of the 11th conductivity type channel MOS transistor and the second conductivity type channel MOS transistor constituting the input section, the well-known back gate bias effect ( !I plate bias effect)
Since the threshold voltages and voltages of each of the MOS transistors connected in a complementary manner can be freely controlled, the circuit threshold voltage of the 0M08 circuit can be freely set. At this time, since the MOS transistors other than the input section are connected normally (the source and the substrate are at the same potential), high speed performance can be maintained. [Embodiments of the Invention] First, before explaining one embodiment of the present invention, the back gate bias effect (substrate bias effect) will be briefly explained. Figure 10 shows the back
FIG. 3 is a diagram showing connections when applying a gate bias. In FIG. 10, a back gate bias voltage VIIG is applied to the n-type semiconductor substrate. At this time, the source is connected to ground potential. As a result, in the n-channel MOS transistor, a voltage is applied in the reverse bias direction between the source and the substrate. FIG. 11 is a diagram quantitatively showing the back gate bias effect. Figure 11'' shows the relationship between the back gate bias and the amount of change ΔVy in threshold voltage when the film thickness t and x of the gate oxide film of an n-channel MOS transistor is 1200A. The attached numbers represent the specific resistance of the substrate.
As can be seen from Figure 1, if the bias voltage is applied between the source and the substrate in the reverse bias direction, the bias voltage VaG
As the threshold voltage increases, the absolute value of the amount of change in the threshold voltage increases. The details of the back gate bias effect are described in detail in, for example, "rMO8/LSI Design and Application" published by Electronics Digest Co., Ltd. An embodiment of the present invention will be described below. Here, we will explain how to provide a 0M08 circuit that can be driven at the TTL level, that is, how to lower the circuit threshold voltage of the 0M08 circuit (bring it closer to Q nd), but conversely, by increasing the circuit threshold voltage <Vc c) can also be easily realized. FIG. 1 is a diagram showing the configuration of an 0M08 circuit according to an embodiment of the present invention. In FIG. 1, p-channel MOS transistor 20 and n-channel MOS transistor 21 are
It forms an inverter circuit that constitutes the input section of MO8 IC, and p-channel MOS transistor 22 and n
The channel MOS transistor 23 is a transistor that constitutes the internal direction Wi. As in the conventional case, voltage VGIIF and voltage VG II N are respectively applied in the reverse bias direction between the sources and substrates of p-channel MOS transistor 20# and n-channel MOS transistor 21. Figure 2 shows the p-channel M that constitutes the input section in Figure 1.
2 is a cross-sectional view of an OS transistor 20 and an n-channel MOS transistor 21. FIG. The structure of the MOS transistors 22 and 23 forming the internal circuit and subsequent parts in FIG. 1 is completely the same as the structure of the conventional MOS transistor shown in FIG.
Further, the same parts as those of the conventional device shown in FIG. 5 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 2, an n-type semiconductor layer 111 epitaxially grown on an n@ semiconductor substrate 105 constitutes a first conductivity type semiconductor substrate 70 together with the n-type semiconductor substrate 105. The p + type buried layer 112 provided at the boundary between the n type semiconductor substrate 105 and the n − type semiconductor layer 111 is ng1
It is formed by diffusing p-type impurities into a predetermined surface region of semiconductor substrate 105, and then re-diffusing the impurities when epitaxially growing n-type semiconductor layer 111. It is formed so as to penetrate through the n-type semiconductor layer 111 and reach the p+-type buried layer 112, and the buried layer 112
A p-type isolation diffusion layer 113 surrounding the upper semiconductor layer 111 serves as a substrate for the n-channel MOS transistor 21.
It is formed simultaneously with the mold island region 106. Separation diffusion layer 113
A p++ seismic region 114 formed on the surface of the p+ type region 109 for applying a back gate bias voltage VG B N is simultaneously formed and connected to a power supply terminal Qnd. p+ type region 1149-type isolation diffusion layer 113 and p+
The mold recess 11112 surrounds a part of the semiconductor substrate 70 and is a second conductivity type isolation region 8 forming a first conductivity type island W4 region 115 separated from the other part of the semiconductor substrate 70.
Configure 0. Source 101 of p-channel MOS transistor 20 and its low IM! ! An electric field JiVG is connected between the plate (island region) 115 in the reverse bias direction (the source potential is lower than the substrate potential).
ap is applied. Further, a voltage VaIIN is also applied between the source 201 of the n-channel MOS transistor 21 and its substrate (island@region) 106 in a reverse bias direction (the source potential is higher than the substrate potential). With such a configuration, in the p-channel MO3)-transistor 20, the potential of the isolation region 80 is the lowest Q.
nd level, the parasitic diodes formed between the semiconductor substrate 70 and the isolation region 80 and between the n'' type island region 115 and the isolation region 80 are both in a reverse bias state, and the p-channel MOS The potential of the n-type island region 115 forming the transistor 20 can be freely changed. Therefore, due to the back gate bias effect, the p
By freely setting the potential of n+ type region 110 with respect to the potential of source 101 of channel MoS transistor 20, threshold voltage VTP of p-channel MOS transistor 20 can be freely changed. Also, in the n-channel MOS transistor 21,
Since the parasitic diode formed between the p-type island region 106 and the n'' type semiconductor substrate 70 is also in a reverse bias state, the potential of the p-type island region 106 can be set freely. Due to the back gate bias effect, the source 10 of the n-channel MOS transistor 21
By freely setting the potential of p+ type region 109 with respect to the potential of MOS transistor 1, the threshold voltage VTN of n-channel MOS transistor 1 can be freely set. The circuit threshold voltage VTHC is the MOS connected in a complementary manner.
Threshold voltage V'T P of transistors 20 and 21
, VTn, so the threshold voltage VTF of each transistor 20 and 21 is adjusted so that the circuit threshold voltage VTHC is between 0.8V and 2°O.
If IVTN is set, 0M can be driven at TTL level.
08 circuit is obtained. FIG. 3 is a diagram showing the input/output voltage and through current characteristics of the circuit of FIG. 1. In FIG. 3, the horizontal axis represents the input voltage v1 applied to the input terminal, and the vertical axis represents the output voltage ``o'' and the through current 1cc. In addition, in the figure, the solid line represents the change in the output voltage v0 with respect to the change in the input voltage V+,
Further, the broken lines indicate changes in the through current Ice with respect to the input voltage V+. As can be seen from FIG. 3, when the input voltage V+ is at a high level VIM (2V), the threshold voltage TP of the p-channel MOS transistor 20 is increased due to the batter gate bias effect, so that the The current (point Y in FIG. 3) is extremely small compared to the conventional circuit shown in FIG. Similarly, the threshold voltage VTM of the n-channel MOS transistor 21 is also
Since it is large due to the bias effect, input 11
Pressure Vrffi O-L/Hair At V I L
(0.8V), the through current (point X in FIG. 3) is smaller than that in FIG. 9. Therefore, compared to the conventional circuit shown in FIG. 4, a circuit with lower power consumption can be provided. In addition, MOS other than the input section) - transistors 22, 23 &
T! 311m-, **ggttr isor, ii[@
' will not be harmed either. In the above embodiment, a 9-type island WI is formed on the n-type semiconductor substrate.
p4 type region in 0MO8・IC that formed I4 region. We have explained the case where a p-type isolation region and an O+ type buried layer are formed, but in the opposite case, that is, an n+ type region and an n-type isolation region are formed in an 0MO8 IC in which an n-type island region is formed on a p-type semiconductor substrate. Also, when an n÷ type buried layer is formed, the same effect as in the above embodiment can be obtained. Further, in the above embodiment, the case where the input section is an inverter circuit has been described, but other NAND circuits, N
A similar effect can be obtained with an OR circuit or the like. Furthermore, although the 0MO3-IC circuit has been described in the above embodiment, the same effect can be obtained in a PiCMOS circuit in which bipolar transistors and MOS transistors coexist on the same chip. [Effect of the invention] As described above, according to the present invention, the p
Only the channel MOS transistor and the n-channel MOS transistor are separated from the transistors that make up all the circuits other than the input section, and a potential difference is created between the substrate and source of each transistor, and due to the back gate bias effect, Only the transistor Q threshold voltage in the human power section is changed. Therefore, as a result, it is possible to freely set the circuit threshold voltage, and it is possible to obtain a semiconductor integrated circuit device with reduced power consumption when a 0MO8 IC and a bipolar logic circuit are used together.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure is a diagram showing a cross-sectional structure of the circuit of FIG. 1. FIG. 3 is a diagram showing the input/output characteristics of the input section of the circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a conventional 0MO8.ICjl small unit. FIG. 5 is a diagram showing a cross-sectional structure of the circuit shown in FIG. 4. FIG. 6 is a diagram showing the input/output characteristics of the circuit shown in FIG. 4. FIG. 7 is a diagram showing an LSTTL circuit used in combination with the C:MOS-IC of FIG. 4. Figure 8 is the 7th
FIG. 3 is a diagram showing input/output characteristics of the circuit shown in the figure. FIG. 9 is a diagram showing the input/output characteristics of the CMO8iC used in combination with the LSTTL circuit shown in FIG. 7. Figure 10 shows p-channel MO
FIG. 3 is a diagram showing a connection configuration when applying a back gate bias to an S transistor. Figure 11 shows p-channel M
FIG. 3 is a diagram quantitatively showing the back gate bias effect of an OS transistor. In the figure, 1, 20.22 are p-channel MOS transistors, 2, 21.23 are n-channel MOS transistors, 80 is an isolation region, 101 is a p9 type source diffusion region,
102 is a p+ type drain diffusion region 201 is an n++ source diffusion region; 202 is an n+ type drain region; 105
is an n-type semiconductor substrate, 106 is a p-type island steel region, and 111 is an n-type semiconductor substrate.
- type semiconductor epitaxial growth layer, 112 is a p+ type buried layer, 113 is a p- type isolation diffusion layer, 114 is a p" type diffusion region, and 115 is an n"" type island region. In addition, in the figure, the same reference numerals are or Indicates the same or equivalent part.

Claims (3)

[Claims] (1) A second conductivity type channel MOS transistor formed on a first conductivity type first semiconductor region and having a first conduction terminal; and a second conductivity type channel MOS transistor formed on a second conductivity type second semiconductor region. A semiconductor integrated circuit device in which a channel MOS transistor of a first conductivity type having a conduction terminal is formed on the same semiconductor substrate and connected in a complementary manner to constitute an input stage, wherein the second semiconductor region of the first conductivity type; and the first conduction terminal; and a first voltage application means for applying a voltage in a reverse bias direction between the second conductivity type second semiconductor region and the second conduction terminal. A semiconductor integrated circuit device, comprising: second voltage application means for applying a voltage. (2) The semiconductor integrated circuit according to claim 1, wherein the second semiconductor region of the second conductivity type is surrounded by a third semiconductor region of the first conductivity type formed in the semiconductor substrate. circuit device. (3) MOs other than the input stage of the semiconductor integrated circuit device
3. The semiconductor integrated circuit device according to claim 1, wherein the sources and substrates of all S transistors are made to have the same potential.