JPS5848957A - Semiconductor output circuit - Google Patents

Abstract

PURPOSE:To obtain the output circuit in which latch-up is difficult to be generated to an external surge by forming the semiconductor output circuit consisting of a CMOS.IC by an NPN bipolar transistor and an NMOS transistor shaped onto one semiconductor substrate. CONSTITUTION:The NPN bipolar transistor 60 and the NMOS transistor 61 are formed to one semiconductor substrate. The circuit is constituted in this manner, the collector 46 of the transistor 60 is connected to line voltage Vcc, an emitter is connected to an output terminal 62 through an Al layer 48, a polycrystal Si resistor 49 and an Al electrode 50, and the drain of the NMOS transistor 61 and a source through an Al electrode 56 are connected between the output terminal 62 and a ground Vss. Signals from an internal circuit 101 formed to the substrate are supplied to the base 47 of the transistor 60 and the gate 54 of the transistor 61, shaped and amplified, and outputted from the terminal 62.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, in the CMO8 integrated circuit structure shown in FIG. An npn bipolar transistor 28 parasitic to the source 17) and a 9MOS transistor (drain 14,
The parasitic pnp transistor 1 (gate 13, source 12) constitutes a pnpn type transistor. At this time, the nMO8MOS transistor/in 4, gate 34, source 5, well 19, well bias high concentration layer 6, 3) forming the output stage and the bipolar transistor (
Base 20, emitter 8, base extraction high concentration layer 7,
When a surge is applied to the output terminal 36 of 9), the base of the npn) run risk 28 is biased to s pnp through the parasitic diode 37 and transistor 38.
The n thyristor was turned on. This on state is called a latch-up state, and must be avoided because a large current flows through the element. When 6 surges are added to 36, the base of transistor 1 is bypassed to a negative voltage through transistor 2, resulting in a latch-up condition as well.

The present invention improves the drawbacks of the conventional CMO8 integrated circuit,
An object of the present invention is to provide an output circuit that is less likely to cause latch-up due to external surges.

The gist of the present invention will be explained below with reference to FIG.

In FIG. 2, the npn bipolar transistor 60 is operated by applying 5 cm of A/ from the pole 46 to the n+ type layer 40.45 formed in the n type Si substrate 39, and the emitter n+ type layer 43 is Resistance of polycrystalline Si layer 49 through layer 48 and nMOS transistor 6 through A/electrode 50
1 drain is connected to the n+ type layer 52. 52 is also connected to an output terminal 62. Furthermore, the base p-type layer 42 of the npn bipolar transistor includes a low resistance p+ type layer 41.
．． A/electrode 47 taken out from 44 is internal circuit 101
The signal is supplied to the Further, a signal is similarly supplied from the internal circuit 101 to the gate electrode 54 of the nMOS transistor.

In FIG. 2, 52 is a p-type well forming nMO8) transistor 1; 51. ．． 57 is p for well bias
+ type layer, 55 is nMO8) source n+ type layer of run lister, 56.58 is A/'[pole.

FIG. 3 compares the circuit of this embodiment with a conventional circuit (a circuit without the resistor 49 in FIG. 2).
= 0, latch-up occurs at a surge voltage of about 100V, but by applying the present invention, latch-up occurs at a surge voltage of about 300V or more.
It can now tolerate surge voltages that are twice as high.

Note that in this embodiment, the resistor ζ has a high surge voltage
Therefore, it is not suitable to form the resistor inside the substrate, such as in a diffusion layer, and it is preferable to form it on the surface of 5i02. For example, if a polycrystalline Si layer used for the gate is used, a resistive layer meeting the desired purpose can be formed, but it goes without saying that the present invention can be applied to any other resistor.

The value of the resistance is desirably 100Ω or less in view of the need to increase the high level voltage at the output terminal and the need to charge the load capacitance at the output terminal at high speed.

For example, in order to achieve a TTL level output amplitude, that is, an output high level VOR>2.4V, considering the bipolar voltage drop of 0.5V, the loss due to resistance must be 2V or less, so when the resistance is 100Ω, IOH is 20mA. acceptable.

The example in which bipolar transistors are used in the output stage has been described above.
．． It has been found that latch-up caused by the surge voltage from the output terminal 66.71 can also be prevented in the output stage using the resistor 64.70 by the same means using the resistor 64.70.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the element structure of the internal circuit section and output circuit section of a conventional CMO8 integrated circuit, and Figure 2 (5)
is a cross-sectional view showing element forgery according to an embodiment of the present invention, and Figure 2 (
H) is a circuit diagram of one embodiment of the present invention, FIG. 3 is a characteristic diagram showing the effects of the present invention, and FIGS. 4 and 5 are circuit diagrams showing other embodiments of the present invention. 46...... Collector electrode of npn bipolar transistor, 47... Base electrode of npn bipolar transistor, 49...
Polycrystalline silicon resistor, 54......nblO
Gate electrode of s transistor, hO...
...npn bipolar transistor, 61...
...... nMO8) Run lister, 62... Song output terminal. Agent Patent Attorney Toshiyuki Usuda 2 Figure (A) 9 (f3 The A? No. 4121 AI May 1 Continuation of page 1 0 Inventor Jikou Uchibori 0 Inventor Norimasa Yasui Josui, Kodaira City 1450 Honmachi Musashi Factory, Hitachi, Ltd.

Claims (1)

[Claims] 1. The collector of the bipolar transistor is connected to the power supply voltage Vc.
C, the emitter and the resistor are connected to the output terminal through a resistor R, the drain and source of the MOS transistor are connected between the output terminal and ground, and other internal circuits are connected to the base of the bipolar transistor and the gate of the MOS transistor. A semiconductor output circuit that is supplied with a signal, shapes and amplifies the signal, and supplies it to an output terminal.