JPS61115319A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS61115319A
JPS61115319A JP59237073A JP23707384A JPS61115319A JP S61115319 A JPS61115319 A JP S61115319A JP 59237073 A JP59237073 A JP 59237073A JP 23707384 A JP23707384 A JP 23707384A JP S61115319 A JPS61115319 A JP S61115319A
Authority
JP
Japan
Prior art keywords
layer
type
layers
thickness
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59237073A
Other languages
Japanese (ja)
Other versions
JPH0738453B2 (en
Inventor
Yoshihiro Hamakawa
圭弘 浜川
Hiroaki Okamoto
博明 岡本
Nobuhiko Fujita
藤田 順彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SEISAN GIJUTSU SHINKO KYOKAI
Original Assignee
SEISAN GIJUTSU SHINKO KYOKAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SEISAN GIJUTSU SHINKO KYOKAI filed Critical SEISAN GIJUTSU SHINKO KYOKAI
Priority to JP59237073A priority Critical patent/JPH0738453B2/en
Publication of JPS61115319A publication Critical patent/JPS61115319A/en
Publication of JPH0738453B2 publication Critical patent/JPH0738453B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To provide a device having a high photoelectric converting efficiency, by laminating alternately amorphous semiconductor layers such as a-Si layers and microcrystalline semiconductor layers such as muc-Si layers. CONSTITUTION:On a substrate 1, a P type layer 2 made of P type a-SiC (amorphous silicon carbide) or P type a-Si, an a-Si layer 3 with thickness of 2,000Angstrom , and a unit laminate 6 consisting of a muc-Si layer 4 and an a-Si layer 5 are formed sequentially. The repeating number (m) of the unit laminate 6 is set at an integer of 1-12. Next to the last layer, an a-Si layer 7 with thickness of 2,000Angstrom and an N type layer 8 made of N type muc-Si are formed. In the range 9, I type layers are being formed. In this way, in a range of 2<=m<=10, a mutau product being higher than that of a single layer can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は非晶質手心体と微結晶質半導体の積層体から
なる半導体素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device comprising a laminate of an amorphous hand core and a microcrystalline semiconductor.

〔従来の技術とその問題点〕[Conventional technology and its problems]

半導体素子の材料として、非晶質シリコン(以下、a−
3iと称する)は、次のような長所と欠点を有する材料
として知られている。
Amorphous silicon (hereinafter referred to as a-
3i) is known as a material having the following advantages and disadvantages.

(長所) (1)低温(250℃以下)で形成できる(2)  低
コスト基板(合成樹脂、ガラス、金属、セラミックス)
が使用できる。
(Advantages) (1) Can be formed at low temperatures (below 250°C) (2) Low-cost substrates (synthetic resin, glass, metal, ceramics)
can be used.

(3)大面積化が容易である。(3) It is easy to increase the area.

(4)  光の吸収係数が大であるため、薄膜で光電変
換素子などが構成できる。
(4) Since the light absorption coefficient is large, photoelectric conversion elements and the like can be constructed using thin films.

(5)光電導度が大である。(5) High photoconductivity.

(欠点) (1)  キャリアの移動度が小さい。(Disadvantage) (1) Carrier mobility is low.

(2)光電変換効率が低い。(2) Low photoelectric conversion efficiency.

一方、微結晶シリコン(以下、μc−8iと称する)は
、次のような長所と欠点を有する材料として知られてい
る。
On the other hand, microcrystalline silicon (hereinafter referred to as μc-8i) is known as a material having the following advantages and disadvantages.

(長所) (11a −S iに比べて、キャリヤ移動度、不純物
ドーピング効率が良い。
(Advantages) (Compared to 11a-Si, carrier mobility and impurity doping efficiency are better.

(2)n型層は、電気伝導度が良く、電導度の活性化エ
ネルギが小さいので、pin構造やショットキー構造の
半導体装置に利用されている。
(2) Since the n-type layer has good electrical conductivity and low activation energy for electrical conductivity, it is used in semiconductor devices having a pin structure or a Schottky structure.

(欠点) (1)  光電導度、午ヤリャの寿命が小さく、かつ欠
陥密度が大であるため、真正層あるいはノンドープ層と
しては利用されていない。
(Disadvantages) (1) Due to the low photoconductivity and low lifetime, and high defect density, it is not used as a true layer or a non-doped layer.

なお、結晶シリコン(以下、c−8iと称する)は、次
のような長所と欠点を有する。
Note that crystalline silicon (hereinafter referred to as C-8i) has the following advantages and disadvantages.

(長所) (1)欠陥が少なく、キャリアの移動度が大である。(Strong Points) (1) Few defects and high carrier mobility.

(2)光電変換素子に応用した場合、大きい光電変換効
率を得ることができる。
(2) When applied to photoelectric conversion elements, high photoelectric conversion efficiency can be obtained.

(欠点) (1)  溶融する必要があるため、製造工程に高温工
程が含まれ、また大面積化が困難である。
(Disadvantages) (1) Since it is necessary to melt, the manufacturing process includes a high temperature step, and it is difficult to increase the area.

(2)光の吸収係数が小さい。(2) The light absorption coefficient is small.

この発明は、a−8i 、  μc−8i 、  c−
8iの上記のごとき緒特性にかんがみ、a−8t  等
の非晶質半導体およびμc−8i  等の微結晶半導体
を用いて好ましい特性、特にμτ積(キャリアの移動度
μと寿命τの積)の大きい半導体素子を提供することを
目的とするものである。
This invention applies to a-8i, μc-8i, c-
In view of the above-mentioned characteristics of 8i, it is desirable to use amorphous semiconductors such as a-8t and microcrystalline semiconductors such as μc-8i to find desirable characteristics, especially the μτ product (product of carrier mobility μ and lifetime τ). The purpose is to provide large semiconductor devices.

〔問題点を解決するための手段〕[Means for solving problems]

この発明は、上記の目的を達成するために、非  □品
質半導体層と微結晶半導体層を交互に一層以上積層した
構成としたものである。
In order to achieve the above object, the present invention has a structure in which one or more non-□ quality semiconductor layers and microcrystalline semiconductor layers are alternately laminated.

上記の非晶質半導体層および微結晶半導体層の一例とし
てa−8i  層およびμc−8i層は、例えば次のご
とき方法によって作られる。
The a-8i layer and the .mu.c-8i layer, which are examples of the amorphous semiconductor layer and the microcrystalline semiconductor layer described above, are made, for example, by the following method.

(1)  プラズマCVD法 少なくともS iH4、SiH6、SiF4 などのS
i化合物ガスを含むガスをグロー放電分解させることに
よりa−3iが得られ、このときSi化合物ガスを水素
などで希釈し、或いはグロー放電分解の際の投入パワー
を大きくすることによりμc−8iが得られる。
(1) Plasma CVD method At least S such as SiH4, SiH6, SiF4
A-3i is obtained by glow discharge decomposition of a gas containing an i compound gas, and at this time, μc-8i can be obtained by diluting the Si compound gas with hydrogen or by increasing the input power during glow discharge decomposition. can get.

(2)  スパッタ法 Si ターゲットを水素、フッ素などを含むガスでスパ
ッターすることによりa−8i  が得られ、このとき
スパッターのパワーを大きくすることによりμc−Si
が得られる。
(2) Sputtering Si A-8i is obtained by sputtering a target with a gas containing hydrogen, fluorine, etc. At this time, by increasing the sputtering power, μc-Si
is obtained.

〔実施例〕〔Example〕

第1図はこの発明の実施例に係る積層半心体素子であり
、基板1から順にp型層−3iまたはp型層−3iC(
非晶質炭化シリコン)でなるp型層2、厚さ200OA
のa−8i層3を形成し、その改番こμc−8i層4と
a−Si層5からなる単位積層体6を形成している。上
記の単位積層体6の繰返し数mを1〜12の整数に定め
、その最終層の次に、順に厚さ200OAのa−8i層
7、n型pc−3iでなるn型層8を形成している。符
号9で示す範囲はi型層を形成する。
FIG. 1 shows a laminated half-core element according to an embodiment of the present invention, in which p-type layer-3i or p-type layer-3iC (
p-type layer 2 made of amorphous silicon carbide, thickness 200OA
A-8i layer 3 is formed, and a unit laminate 6 consisting of a μc-8i layer 4 and an a-Si layer 5 is formed. The number m of repetitions of the above unit laminate 6 is set to an integer from 1 to 12, and next to the final layer, an a-8i layer 7 with a thickness of 200 OA and an n-type layer 8 made of n-type PC-3i are formed in order. are doing. The area indicated by reference numeral 9 forms an i-type layer.

上記i型層9の全体の厚みは6000Xであり、ttc
−8i層4の厚さμ、は50Xである。a−8i層5厚
さad とすると、m、μ 、adは次の関係がある。
The total thickness of the i-type layer 9 is 6000X, and ttc
The thickness μ of the -8i layer 4 is 50X. When the thickness of the a-8i layer 5 is ad, m, μ, and ad have the following relationship.

”(Ad+ad)=200OA なお、この発明は、少なくとも上記の単位積層体5(m
=1〜12)によって構成される。
”(Ad+ad)=200OA Note that the present invention provides at least the unit laminate 5 (m
= 1 to 12).

第2図は、繰返し数mに対するキャリア(正孔と電子)
のμγ積の総和を黒丸で示している。また、比較のため
に、単層のa−3i層(いずれも6000X)の場合を
白丸で示している。
Figure 2 shows carriers (holes and electrons) for the number of repetitions m.
The sum of the μγ products of is shown by a black circle. For comparison, the case of a single a-3i layer (both 6000X) is shown by a white circle.

この結果、2≦m≦10の範囲で、単層のものより高い
μτ積が得られることがわかった。
As a result, it was found that in the range of 2≦m≦10, a higher μτ product than that of a single layer can be obtained.

なお、i型層9の両端のa−8i層3.7の厚さをそれ
ぞれ100〜5000A の籟囲とすること、a を5
0〜1000Åとすることμ、を20〜500Aとする
ことができる。
In addition, the thickness of the a-8i layers 3.7 at both ends of the i-type layer 9 should be 100 to 5000A, and a should be 5.
By setting it to 0 to 1000 Å, μ can be set to 20 to 500 A.

〔効 果〕〔effect〕

この発明は、上記のように、a−8i層等の非晶質半導
体層とμc−8i層等の微結晶半導体層を交互に一層以
上積層した構成とすることにより、キャリアのμτ積を
大きくすることができ、この結果、光起電力素子や発光
素子に使用した場合に、光電変換効率の高い素子を得る
ことができる。また、キャリアの移動速度が大であるた
め、薄膜トランジスタや光電等素子に使用した場合応答
速度の速い素子を得ることができる。
As described above, this invention has a structure in which one or more amorphous semiconductor layers such as an a-8i layer and one or more microcrystalline semiconductor layers such as a μc-8i layer are laminated alternately, thereby increasing the μτ product of carriers. As a result, when used in a photovoltaic element or a light emitting element, an element with high photoelectric conversion efficiency can be obtained. Furthermore, since the moving speed of carriers is high, when used in thin film transistors, photoelectric devices, etc., devices with high response speed can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は実施例の半導体素子の積層構造を拡大して示し
た説明図、第2図は実験結果のグラフである。 1・・・基板、2・・・p型層、3・・・a−8i層、
4・・・μc−3i層、5・・・a−3i層、6・・・
単位積層体、7・・・a−8i層、8・・・n型層、9
・−・i型層→ μτ(ol/V)
FIG. 1 is an explanatory diagram showing an enlarged stacked structure of a semiconductor device according to an example, and FIG. 2 is a graph of experimental results. DESCRIPTION OF SYMBOLS 1... Substrate, 2... P-type layer, 3... A-8i layer,
4...μc-3i layer, 5...a-3i layer, 6...
Unit laminate, 7... a-8i layer, 8... n-type layer, 9
・-・I-type layer → μτ (ol/V)

Claims (8)

【特許請求の範囲】[Claims] (1)非晶質半導体層と微結晶半導体層を交互に一層以
上積層してなる半導体素子。
(1) A semiconductor device formed by alternately stacking one or more amorphous semiconductor layers and microcrystalline semiconductor layers.
(2)非晶質半導体層と微結晶半導体層の構成元素とし
て少なくともSiを含む特許請求の範囲第1項に記載の
半導体素子。
(2) The semiconductor device according to claim 1, wherein the amorphous semiconductor layer and the microcrystalline semiconductor layer contain at least Si as a constituent element.
(3)非晶質半導体層の厚みが50〜1000Åである
特許請求の範囲第1項または第2項に記載の半導体素子
(3) The semiconductor device according to claim 1 or 2, wherein the amorphous semiconductor layer has a thickness of 50 to 1000 Å.
(4)微結晶半導体層の厚みが20〜1000Åである
特許請求の範囲第1項から第3項のいずれかに記載の半
導体素子。
(4) The semiconductor device according to any one of claims 1 to 3, wherein the microcrystalline semiconductor layer has a thickness of 20 to 1000 Å.
(5)積層部分の基板側に非晶質半導体層を設けた特許
請求の範囲第1項から第4項のいずれかに記載の半導体
素子。
(5) The semiconductor device according to any one of claims 1 to 4, wherein an amorphous semiconductor layer is provided on the substrate side of the laminated portion.
(6)積層部分の基板側に設けた非晶質半導体層の厚み
が100〜5000Åである特許請求の範囲第5項に記
載の半導体素子。
(6) The semiconductor device according to claim 5, wherein the amorphous semiconductor layer provided on the substrate side of the laminated portion has a thickness of 100 to 5000 Å.
(7)積層部分の基板と反対側に非晶質半導体層を設け
た特許請求の範囲第1項から第6項のいずれかに記載の
半導体素子。
(7) The semiconductor device according to any one of claims 1 to 6, wherein an amorphous semiconductor layer is provided on the opposite side of the laminated portion from the substrate.
(8)積層部分の基板と反対側に設けた非晶半導体層の
厚みが100〜5000Åである特許請求の範囲第7項
に記載の半導体素子。
(8) The semiconductor device according to claim 7, wherein the amorphous semiconductor layer provided on the side opposite to the substrate of the laminated portion has a thickness of 100 to 5000 Å.
JP59237073A 1984-11-10 1984-11-10 Stacked semiconductor device Expired - Lifetime JPH0738453B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59237073A JPH0738453B2 (en) 1984-11-10 1984-11-10 Stacked semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59237073A JPH0738453B2 (en) 1984-11-10 1984-11-10 Stacked semiconductor device

Publications (2)

Publication Number Publication Date
JPS61115319A true JPS61115319A (en) 1986-06-02
JPH0738453B2 JPH0738453B2 (en) 1995-04-26

Family

ID=17010012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59237073A Expired - Lifetime JPH0738453B2 (en) 1984-11-10 1984-11-10 Stacked semiconductor device

Country Status (1)

Country Link
JP (1) JPH0738453B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010034525A (en) * 2008-06-25 2010-02-12 Fuji Electric Holdings Co Ltd Thin-film solar cell
JP2010287880A (en) * 2009-06-12 2010-12-24 Korea Iron & Steel Co Ltd Photovoltaic device, and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010034525A (en) * 2008-06-25 2010-02-12 Fuji Electric Holdings Co Ltd Thin-film solar cell
JP2010287880A (en) * 2009-06-12 2010-12-24 Korea Iron & Steel Co Ltd Photovoltaic device, and method of manufacturing the same
US8642115B2 (en) 2009-06-12 2014-02-04 Kisco Photovoltaic device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0738453B2 (en) 1995-04-26

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