JPS61113253A - Testing process of semiconductor - Google Patents

Abstract

PURPOSE:To speed up the testing time eliminating any stand-by time by a method wherein the surface of integrated circuit element is irradiated with light for specified period of time during the successive tests for different voltage to be impressed. CONSTITUTION:When a test for march pattern at an impressed voltage Vcc=7V is performed in e.g. a testing process 8, the potential of node 8 will be 9.5V. As programed in the next irradiation process 9, a light source 6 is lighted for e.g. 10msec to irradiate an integrated circuit element to be tested with light 7. The voltage on node B may be lowered by the irradiation as shown in the solid lines. As soon as the voltage on node B is sufficiently lowered, start the testing process 10 to test for a checker board pattern e.g. Vcc=4V. Resultantly the circuit may work normally in the testing process eliminating any stand-by time for the process 10.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a semiconductor testing method for selecting good and defective integrated circuit devices from a semiconductor wafer in which a plurality of semiconductor circuit devices are configured in the form of a wafer. The present invention relates in particular to improvements in semiconductor testing methods in which tests are successively carried out under different applied voltages.

C. Prior Art] In general, in semiconductor integrated circuits, multiple chips are formed on a semiconductor wafer at the same time, and since good and defective chips coexist among them, the chips must first be tested in the wafer state before being encapsulated in a package. We carry out tests to select only good products. In this test, in order to also check the chip's electrical characteristic margin, it is usually performed by applying a voltage within a fairly wide range relative to the specified power supply voltage. For example, while the standard value of the power supply voltage of the dynamic RAM 64 and 256 is 5v±0.5v, in the test, a power supply voltage in the range of approximately 3.5v to 8v is applied.

Various power supply voltages (Vcc
), the important thing to keep in mind when testing is the sequence of test voltages. Voltage sequences in which Vcc changes by as much as 3V without too much time interval must be avoided, such as testing with a march pattern of Vcc = 7V and immediately testing with a checkerboard pattern of Vcc = 4V. . The reason for this is
This is because when tested under such large changes in applied voltage, the chip may malfunction even though it is originally a good product, or the signal transmission time may be delayed more than necessary.

Next, the mechanism of this malfunction will be explained using an example of one circuit. FIG. 4 is a circuit diagram showing a bootstrap circuit often used in dynamic RAM and the like. The operation of this circuit will be explained using FIG. Node B in Figure 4
is Vcc if the bootstrap works in period T1.
-V clove α (V). Here, α is usually a value of about Vcc/2 to VCC, and VT is the threshold voltage of the MOS transistor making up this circuit. Now, the value of α is Vcc/2. If VT=IV, Vcc=7V
(7) At 8 points, the node becomes 9.5V. During this period, the voltage at node A is Ov, so Ql is in a non-conducting state,
Since only Ql is in a conductive state, the voltage of note C becomes 7V.

Next, in period T2, the voltage at node A changes from Ov to Vcc (=7
V). At this time, Q2 conducts and Ql
, Ql are both in a conductive state. The gate voltages of Ql and Ql at this time are Vcc-VT and Vcc, respectively.

On the other hand, the transistor size of Ql and Ql is usually 1:5
The gm ratio of Ql and Ql is approximately 1:
5, so the voltage at node C becomes approximately Ov.

The above explanation is based on the case where the bootstrap circuit works normally, but below, the case where the test is performed with Vcc=7V and then with Vcc=4V as described above will be explained.

In this case, the voltage at node B is 9.5V in period T1 when tested at Vcc=7V. Next, Vcc=4
The normal node B voltage when it reaches V is 5. Ov, but once node B becomes 9.5V, even if Vcc changes to 4V, Q3 becomes non-conductive, so this voltage (9.5V) is held at node B. It will be done. Therefore, at the beginning of one period T2, Ql and Ql
The gate voltages of will be 9.5v and 4v. Therefore, the transistor size. l and. Even if the ratio is 1:5 with 2,
The gate voltage of Ql. Because it is higher than that of 2,
The effective gm ratio becomes smaller. Therefore, the voltage change at node C may be delayed as shown in waveform C, or in the worst case, waveform C
As shown in , it is possible that the voltage will be intermediate, causing the circuit to malfunction.

[Problem to be Solved by the Invention 3 As described above, in the conventional semiconductor testing method, when performing a test with a high power supply voltage (Vcc) applied, and then a test with a low Vcc voltage applied, It is necessary to wait until the voltage at node B in FIG. 4 drops, and this time is extremely long, especially in tests at room temperature, resulting in a drawback that the test takes a long time.

The present invention has been made to eliminate the above-mentioned drawbacks and aims to provide a method for testing semiconductors that allows testing to be performed very quickly without requiring any waiting time between tests at different voltages. The purpose is

[Means for Solving the Problems] The semiconductor testing method according to the present invention includes a step of irradiating the surface of an integrated circuit element with light for a predetermined period of time between tests under successive applications of different voltages. This is what I did.

[Function] Electrons generated by irradiating the surface of the integrated circuit element with light drift into the revised region forming node B, thereby quickly dropping the voltage held there by the previous high voltage application test. This makes it possible to perform the next test by applying low voltage.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a schematic configuration diagram showing an example of a test apparatus for carrying out the test method of the present invention, and FIG. 2 is a process diagram showing an embodiment of the present invention.

In the figure, (1) is a probe card, (2) is a needle-like electrode attached to this probe card (1), which is made to contact the pad provided on the surface of the integrated circuit element, and (3) is a needle-shaped electrode attached to the probe card (1). A semiconductor wafer (4) on which a plurality of integrated circuit elements are formed is a chuck top that supports the semiconductor wafer (3) by adsorbing it. (5) is a microscope used for positioning each integrated circuit element and the needle-like electrode (2); (6) is a light source for illuminating the surface of the integrated circuit element that is blinked by a program installed in the microscope (5); (7) is its irradiation light.

Next, the test process shown in FIG. 2 according to this embodiment will be explained with reference to FIG. 3 for the circuit example shown in FIG. 4.

FIG. 3 is a time chart showing voltage changes at nodes A, B, and C of the circuit shown in FIG. 4 in each step of this embodiment. The solid line is when light irradiation is performed, and the broken line is when light irradiation is not performed. It shows.

First, in step (8) of FIG. 2, the applied voltage Vcc=
A march pattern test was performed at 7V, and at the end of the test, the potential at node B in FIG. 4 was 9.5V. 10m as programmed in the next step (9)
The light source (6) is turned on for 5 ec and the light (7) is irradiated onto the integrated circuit element under test. By this light irradiation, electron-hole pairs are generated at the p-n junction formed on the surface of the integrated circuit element, and as the electrons drift into the n+ region forming node B, they approach a thermal equilibrium state. Therefore, during this 10 m5 ec light irradiation time, the voltage at node B drops as shown by the third solid line. When the voltage at node B has dropped sufficiently, step (10) is entered and Vcc=4
Begin testing with a checkerboard pattern at V. Therefore, the circuit operates normally in this test step (10).

In the above embodiments, a microscope is used as a light source for light irradiation, but a separate light source may be provided. Moreover, if a light emitting diode is used as this separate light source, light irradiation can be performed for a short time with better controllability.

[Effects of the Invention] Since the present invention is carried out as described above, when testing a semiconductor wafer, it becomes easy to perform tests under large power supply voltage changes, making it possible to perform more severe tests and shortening the test time. There is an effect that can be done.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram showing an example of a test device for carrying out the test method of the present invention, Fig. 2 is a process diagram showing an embodiment of the invention, and Fig. 3 is an integration diagram in each step of this embodiment. FIG. 4 is a flowchart showing voltage changes at various parts of the circuit elements, FIG. 4 is a circuit diagram showing an example of an integrated circuit to be tested according to the present invention, and FIG. 5 is an explanatory diagram of the operation of the circuit shown in FIG. 4. In the figure, (3) is a semiconductor wafer, (6) is a light source for light irradiation, (8) and (10) are test steps performed by applying different voltages, and (9) is a light irradiation step. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (3)

[Claims] (1) In a semiconductor testing method that sequentially tests each integrated circuit element of a semiconductor wafer consisting of a plurality of integrated circuit elements while sequentially applying different voltages, and selects good and defective integrated circuit elements. . A method for testing a semiconductor, comprising the step of irradiating the surface of each integrated circuit element with light for a predetermined period of time between the tests under the successive application of different voltages. (2) The method for testing a semiconductor according to claim 1, wherein a light source of a microscope for aligning integrated circuit elements is used to irradiate the light. (3) The method for testing a semiconductor according to claim 1, wherein a light emitting diode is used as a light source for irradiating the light.