JPS61112386A - Semiconductor light receiving element - Google Patents
Semiconductor light receiving elementInfo
- Publication number
- JPS61112386A JPS61112386A JP59233160A JP23316084A JPS61112386A JP S61112386 A JPS61112386 A JP S61112386A JP 59233160 A JP59233160 A JP 59233160A JP 23316084 A JP23316084 A JP 23316084A JP S61112386 A JPS61112386 A JP S61112386A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- receiving element
- light receiving
- type inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 18
- 229910004205 SiNX Inorganic materials 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000002230 thermal chemical vapour deposition Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 102100022026 Pregnancy-specific beta-1-glycoprotein 6 Human genes 0.000 abstract 1
- 108010044665 pregnancy-specific beta-1-glycoprotein 12 Proteins 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 230000032683 aging Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
- H01L31/1035—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、受光素子の表面安定化に係り、特に暗電流低
減に好適なパッシベーション方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to surface stabilization of a light receiving element, and particularly to a passivation method suitable for reducing dark current.
従来の長波受光素子のパッシベーションには、昭和５９
年応用物理学会春期年会予稿集３１Ｐ−Ｌ−１や３１Ｐ
−Ｌ−２にみられるようにＳｉＮｘのみが用いられてい
た。しかし、ＳｉＮｘと半導体との熱膨張係数が異なる
ため、Ｓ ｉ Ｎ ｘ単独では高温エージング時に膜は
がれやクラックが生じ易いこと、薄い場合にはピンホー
ルが発生すること等のため、暗電流が増加してしまう欠
点があった。The passivation of conventional long-wave photodetectors was developed in 1982.
Proceedings of the Japan Society of Applied Physics Spring Annual Meeting 31P-L-1 and 31P
As seen in -L-2, only SiNx was used. However, because the thermal expansion coefficients of SiNx and semiconductors are different, SiNx alone tends to peel or crack during high temperature aging, and if it is thin, pinholes may occur, resulting in an increase in dark current. There was a drawback to it.
本発明の目的は、上記従来の問題を解決し、受光素子に
対して良好な表面不活性化効果を示すパッシベーション
膜を提案し、信頼性の高い半導体受光素子を提供するこ
とにある。An object of the present invention is to solve the above-mentioned conventional problems, to propose a passivation film that exhibits a good surface passivation effect on a photodetector, and to provide a highly reliable semiconductor photodetector.
上記目的を達成するため、本発明では受光素子のパッシ
ベーション膜としてＳｉＮｘ、ＰＳＧ（リン含有ガラス
）＋ Ｓ ｉ０２ の三層構造を採用したことを特徴と
する。In order to achieve the above object, the present invention is characterized in that a three-layer structure of SiNx, PSG (phosphorus-containing glass) + Si02 is adopted as a passivation film of a light receiving element.
それにより、高温エージング試験を実施しても、暗電流
が増加したり１時間とともに変化する現像を抑えること
が可能となり、信頼性の高い受光素子を得ることができ
る。Thereby, even if a high-temperature aging test is performed, it is possible to suppress an increase in dark current or a change in development over an hour, and a highly reliable light-receiving element can be obtained.
なお、一般にはＳ ｉ Ｎｘ （１，３３≦ｘ≦２）お
よびＰ含有率５モルパーセントのＰＳＧを多用する。In general, Si Nx (1,33≦x≦2) and PSG with a P content of 5 mol percent are frequently used.
パッシベーション膜の各層は下記の厚さとなすが好適で
ある。薄過ぎることにより生じるピンホール及び厚過ぎ
ることにより生じるクラックを抑えるために、Ｓ ｉ
Ｎ ｘ １０００〜４０００人、ＰＳＧ２０００〜６０
００人、 Ｓ ｉ ０．２０００〜６０００人を通常用
いる。It is preferable that each layer of the passivation film has the following thickness. In order to suppress pinholes caused by being too thin and cracks caused by being too thick, Si
N x 1000-4000 people, PSG 2000-60
00 people and S i 0.2000 to 6000 people are usually used.
以下、本発明を実施例を参照にして詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
実施例 第１図を用いて本発明を説明する。Example The present invention will be explained using FIG.
第１図（ａ）はプレーナ型ホトダイオードを示す。ｎ型
ＩｎＰ基板１の上にｎ型ＩｎＰ層２．ｎ層ＩｎＧａＡｓ
Ｐ層３．ｎ層ＩｎＰ層４．ｎ型ＩｎＧａＡｓＰ層５を結
晶成長させる。次にｎ型ＩｎＰ層３にＺｎ拡散を行ない
ｐ型ＩｎＰ層６を形成した後パッシベーション７を行な
う。次に、ｎ型電極ＡｕＧｅＮｉ／ Ｐ ｄ ／ Ａ
ｕ ９ ｒ Ｐ型電極Ｔ ｉ ／ Ｐ ｔ ／Ａ ｕ
８を形成する。パッシベーション膜７は詳細には第１図
（ｂ）に示すように三層構造をとる。FIG. 1(a) shows a planar photodiode. An n-type InP layer 2. is formed on the n-type InP substrate 1. n-layer InGaAs
P layer 3. n-layer InP layer 4. The n-type InGaAsP layer 5 is crystal-grown. Next, Zn is diffused into the n-type InP layer 3 to form a p-type InP layer 6, and then passivation 7 is performed. Next, the n-type electrode AuGeNi/Pd/A
u 9 r P-type electrode T i /P t /A u
form 8. Specifically, the passivation film 7 has a three-layer structure as shown in FIG. 1(b).
第一層はプラズマＣＶＤを用いたシリコン・ナイＩ−ラ
イド（ＳｉＮｘ）１１を１０００人被着する６第二層は
熱ＣＶ Ｄ （Ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ Ｄｅ
ｐｏｓｉｔｉｏｎ）によってＰＳＧ （リン含有５ｉｎ
２）１２を２０００人被着する。第三層は熱ＣＶＤによ
ってＳｉ○２１３を２０００人被着する。The first layer is silicon nitride (SiNx) 11 coated with 1000 layers using plasma CVD.6 The second layer is a thermal CVD (Chemical Vapor De
PSG (phosphorus containing 5in
2) Cover 2,000 people with 12. The third layer is formed by depositing 2000 Si213 layers by thermal CVD.
上記のように作製したホトダイオードの高温エージング
試験（１２５℃、３０ｖバイアス）を行なうと、１００
０時間以上でも暗電流の劣化は生じなかった。A high temperature aging test (125°C, 30V bias) of the photodiode fabricated as described above revealed that 100%
No deterioration of dark current occurred even after 0 hours or more.
従来のパッシベーション法（ＳｉＮｘ単独、あるいはＳ
ｉｎ、等）で作成した素子の上記試験では、１００時間
を経過すると暗電流特性に劣化が見られるのに対し、本
発明により安定化できた。 、ｌｘ第１図を用
いて実施例を述べたが、第１図で３のＩｎＧａＡｓＰ層
をＩｎＧａＡｓにした場合、５のＩｎＧａＡｓＰ層がな
く直接４，６層上にパッシベーション膜を形成した場合
においても１本発明の本質をそこなうものではない。Traditional passivation methods (SiNx alone or S
In the above test of the device fabricated using 100 hours, the dark current characteristics deteriorated after 100 hours, but the present invention stabilized the dark current characteristics. , lx An example has been described using FIG. 1, but even if the InGaAsP layer 3 is made of InGaAs in FIG. 1. This does not impair the essence of the present invention.
また、第２図に示すようなホモジャンクション素子、第
３図に示すようなＧ ａ Ａ ｓを利用した素子の場合
、あるいは他の化合物半遵体材料素子においても本発明
が適用できることは明らかである。Furthermore, it is clear that the present invention can be applied to homojunction devices as shown in FIG. 2, devices using GaAs as shown in FIG. 3, or other compound semiconducting material devices. be.
第２図はホモ接合ホトダイオードを示す。FIG. 2 shows a homojunction photodiode.
ｎ型ＩｎＰ基板２１の上にｎ−−ＩｎＰ層２２゜ｎ −
−ＩｎＧａＡｓ層２３を結晶成長させる。An n--InP layer 22°n- is formed on the n-type InP substrate 21.
- The InGaAs layer 23 is grown as a crystal.
次に、ＩｎＧａＡｓ層２３にＺｎ拡散を行ない、ｐ−Ｉ
ｎＧａＡｓ層２４を形成した後、プラズマＣＶＤＳｉＮ
ｘ、熱ＣＶＤ ＰＳＧ、熱ＣＶＤ Ｓｉｎ。Next, Zn is diffused into the InGaAs layer 23, and p-I
After forming the nGaAs layer 24, plasma CVDSiN
x, thermal CVD PSG, thermal CVD Sin.
三層構造を持つパッシベーション２５を行なう。Passivation 25 having a three-layer structure is performed.
次に、ｐ型電極Ｔｉ／Ｐｔ／Ａｕ２６．ｎ電極ＡｕＧｅ
Ｎｉ／ Ｐ ｄ ／ Ａ ｕ ２７を形成する。Next, a p-type electrode Ti/Pt/Au26. n-electrode AuGe
Form Ni/Pd/Au27.
第３図はＧａＡｓ基板上に作製したホトダイオードを示
す。FIG. 3 shows a photodiode fabricated on a GaAs substrate.
ＧａＡｓ基板３１上にｎ−ＧａＡｓ層（３２）。An n-GaAs layer (32) on the GaAs substrate 31.
ｎ−−ＧａＡｓ層（３３）、ｎ−ＧａＡＱＡｓ層（３４
）。n--GaAs layer (33), n-GaAQAs layer (34)
).
ｎ −−Ｇ ａ Ａ ｓ層（３６）を結晶成長させる。The n--G a As layer (36) is crystal-grown.
次に、ｎ −−ＧａＡ Ｑ Ａｓ窓層にＺｎ拡散を行な
い、ｐ−ＧａＡＱＡｓ層（３５）を形成する。ひき続き
プラズマＣＶＤ ＳｉＮｘ／ＰＳＧ／ＳｉＯ，三層構
造のパッシベーション膜（３７）を形成する。最後にｐ
型電極としてＴ ｉ ／ Ｐ ｔ ／ Ａ ｕ （３８
）、ｎ型電極としてＡｕＧｅＮｉ／ Ｃｒ ／ Ａ ｕ
を形成する。Next, Zn is diffused into the n--GaAQAs window layer to form a p-GaAQAs layer (35). Subsequently, a passivation film (37) having a three-layer structure of SiNx/PSG/SiO is formed by plasma CVD. Finally p
T i / P t / A u (38
), AuGeNi/Cr/Au as n-type electrode
form.
本発明によれば、高温エージング試験に十分耐え得る信
頼性の高い半導体受光素子が得られる。According to the present invention, a highly reliable semiconductor light receiving element that can sufficiently withstand high temperature aging tests can be obtained.
素子の信頼性の向上に伴ない、歩留りも改善され、その
経済的利益は大きい。As the reliability of devices improves, yields also improve, and the economic benefits are significant.
受光素子の高速動作を実現するには寄生容量、特にパッ
ド容量を低減することが必要である。ｐ型電極８に対応
するパッド容量はパッシベーション膜の厚さに逆比例す
る。従来用いられてきた方法ではクラックが発生するた
めにＳ ｉ Ｎ ｘの厚さの上限は約０．５ μｍで
あった。本発明の三層構造を用いるとパッシベーション
膜厚を１．５ μｍにすることが可能であり、パッド容
量を１／３に低減することができる。In order to realize high-speed operation of a light receiving element, it is necessary to reduce parasitic capacitance, especially pad capacitance. The pad capacitance corresponding to the p-type electrode 8 is inversely proportional to the thickness of the passivation film. In conventional methods, the upper limit of the thickness of S i N x was about 0.5 μm because cracks would occur. By using the three-layer structure of the present invention, the passivation film thickness can be reduced to 1.5 μm, and the pad capacitance can be reduced to ⅓.
第１図（ａ）はＩｎＰ系ＰＩＮホトダイオードの断面図
、第１図（ｂ）は第１部７のパッシベーション膜部の断
面図である。第２図はＧａ、Ｉｎ、−ヨＡｓ（Ｘ二０．
４７）ホモ接合ＰＩＮホトダイオードを示す断面図、第
３図はＧａＡＱＡｓ ／Ｇ ａ Ａ ｓヘテロ接合ＰＩ
Ｎホトダイオードを示す断面図である。
１−ｎ”−ＩｎＰ基板、２−ｎ−ＩｎＰ （１，５μｍ
） 、 ３−ｎ −ＩｎＧａＡｓＰ （１，５ｐｍ）
、 ４・−ｎ −１ｎ Ｐ （２μｍ） 、 ５＝・
ｎ −ＩｎＧａＡｓＰ （０，３ａｍ１．６・＝ｐ−Ｉ
ｎＰ、７−８ｉＯ，／ＰＳＧ／ＳｉＮｘ （０，６μｍ
）、８−ｐ電極（Ｔｉ／Ｐ ｔ ／ Ａ ｕ ） 、
９ ・・・ｎ電極（ＡｕＧｅＡｕ／ Ｐ ｄ ／ Ａ
ｕ ）、１１、−８ｉＮｘ （０，１５、ｌＺｍ）、
１２−ＰＳＧ（０，２５μｍ）、１３−８ｉｎ２ （０
，２μｍ）、２］−ｎ”−ＩｎＰ基板、２２−ｎ−−Ｉ
ｎＰ（１，５μｍ） 、 ２３・”ｎ−−Ｉｎａ、５ａ
Ｇａｏ、４ｔＡＳ（１，５７１ｍ） 、 ２４・＝ｐ−
Ｉｎｎ、５ｉＧａｏ、４ｔ＾Ｓ、２５ ・・・Ｓ ｉＯ
ｘ ／ Ｐ Ｓ Ｇ ／ Ｓ ｘ Ｎ ｘ （０、６ｔ
ｔ ｒｎ ）、２６− ｐ電極（Ｔ ｉ ／ Ｐ ｔ
／ Ａ ｕ ） 、 ２７− ｎ電極（ＡｕＧａＮｉ／
Ｐ ｄ ／ Ａ ｕ ）、３１−ｎ”−ＧａＡｓ基板
、 ３２−ｎ−−Ｇ ａ Ａ ｓ （２μｍ） −３３
−・ｎ−−ＧａＡｓ （２μｍ） 、 ３４−ｎ−
ＧａＡＱＡｓ 。
（１，５μｍ）、 ３５・＝ｐ ＧａＡｌ２Ａｓ
、 ３６ ・・・ｎ−−Ｇ ａ Ａｓ （０，５μｍ
）、 ３７＝Ｓ ｉ Ｏ。
／ＰＳＧ／５ｉＮｘ（０，６μｒｎ）、３８・−ｐ電極
（Ｔｉ／Ｐｔ／Ａｕ）、３９−ｎ電極（ＡｕＧｅＡｕ
／第１図（久） ′
冨 Ｚ 図
１３ 図FIG. 1(a) is a cross-sectional view of an InP-based PIN photodiode, and FIG. 1(b) is a cross-sectional view of the passivation film portion of the first portion 7. As shown in FIG. Figure 2 shows Ga, In, -yoAs (X20.
47) Cross-sectional view showing a homojunction PIN photodiode, Figure 3 shows a GaAQAs/GaAs heterojunction PI
FIG. 3 is a cross-sectional view showing an N photodiode. 1-n”-InP substrate, 2-n-InP (1.5 μm
), 3-n-InGaAsP (1,5pm)
, 4・-n −1n P (2μm) , 5=・
n-InGaAsP (0,3am1.6・=p-I
nP,7-8iO,/PSG/SiNx (0.6μm
), 8-p electrode (Ti/Pt/Au),
9...n electrode (AuGeAu/Pd/A
u ), 11, -8iNx (0,15, lZm),
12-PSG (0,25μm), 13-8in2 (0
, 2 μm), 2]-n''-InP substrate, 22-n--I
nP (1,5 μm), 23・”n--Ina, 5a
Gao, 4tAS (1,571m), 24・=p-
Inn, 5iGao, 4t^S, 25...S iO
x / P S G / S x N x (0,6t
trn), 26-p electrode (Ti/Pt
/Au), 27-n electrode (AuGaNi/
Pd/Au), 31-n''-GaAs substrate, 32-n--GaAs (2 μm) -33
-・n--GaAs (2μm), 34-n-
GaAQAs. (1.5 μm), 35・=p GaAl2As
, 36...n--G a As (0.5 μm
), 37=S i O. /PSG/5iNx (0,6μrn), 38-p electrode (Ti/Pt/Au), 39-n electrode (AuGeAu
/Figure 1 (Ku) ′ Tomi Z Figure 13 Figure
Claims (1)
ｘの三層構造を有することを特徴とする半導体受光素子
。 ２、上記受光素子は少なくともＩｎ＿ｘＧａ＿１＿−＿
ｘＡｓ＿ｙＰ＿１＿−＿ｙ（０≦ｘ≦１、０≦ｙ≦１）
を受光用活性領域に用いたことを特徴とする特許請求の
範囲第１項記載の半導体受光素子。 ３、上記三層構造の厚さを各々ＳｉＮｘ１０００〜４０
００ÅＰＳＧ２０００〜６０００Å、ＳｉＯ＿２２００
０〜６０００Åとした特許請求の範囲第１項又は第２項
記載の半導体受光素子。[Claims] 1. SiO_2/PSG/SiN in passivation film
A semiconductor light-receiving element characterized by having a three-layer structure of x. 2. The light receiving element is at least In_xGa_1_-_
xAs_yP_1_-_y (0≦x≦1, 0≦y≦1)
2. A semiconductor light-receiving device according to claim 1, characterized in that a light-receiving active region is made of: 3. The thickness of the above three-layer structure is SiNx1000~40
00ÅPSG2000~6000Å, SiO_2200
A semiconductor light-receiving element according to claim 1 or 2, wherein the thickness is 0 to 6000 Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233160A JPH0758800B2 (en) | 1984-11-07 | 1984-11-07 | Semiconductor light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233160A JPH0758800B2 (en) | 1984-11-07 | 1984-11-07 | Semiconductor light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112386A true JPS61112386A (en) | 1986-05-30 |
| JPH0758800B2 JPH0758800B2 (en) | 1995-06-21 |
Family
ID=16950657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59233160A Expired - Lifetime JPH0758800B2 (en) | 1984-11-07 | 1984-11-07 | Semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758800B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011131000A1 (en) * | 2010-04-20 | 2011-10-27 | 常州天合光能有限公司 | Method for achieving graded lamination passivation thin film on backplane of solar battery |
| CN110911499A (en) * | 2019-09-27 | 2020-03-24 | 北京时代民芯科技有限公司 | Glass-sealed voltage regulating diode, tube core and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588337A (en) * | 1978-12-27 | 1980-07-04 | Nippon Denso Co Ltd | Manufacture of semiconductor device |
| JPS5617025A (en) * | 1979-07-20 | 1981-02-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPS57139930A (en) * | 1981-02-24 | 1982-08-30 | Nec Corp | Semiconductor device |
-
1984
- 1984-11-07 JP JP59233160A patent/JPH0758800B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588337A (en) * | 1978-12-27 | 1980-07-04 | Nippon Denso Co Ltd | Manufacture of semiconductor device |
| JPS5617025A (en) * | 1979-07-20 | 1981-02-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPS57139930A (en) * | 1981-02-24 | 1982-08-30 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011131000A1 (en) * | 2010-04-20 | 2011-10-27 | 常州天合光能有限公司 | Method for achieving graded lamination passivation thin film on backplane of solar battery |
| CN110911499A (en) * | 2019-09-27 | 2020-03-24 | 北京时代民芯科技有限公司 | Glass-sealed voltage regulating diode, tube core and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758800B2 (en) | 1995-06-21 |
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