JPS61111216U

JPS61111216U -

Info

Publication number: JPS61111216U
Application number: JP20121484U
Authority: JP
Priority date: 1984-12-25
Filing date: 1984-12-25
Publication date: 1986-07-14

Description

[Brief explanation of the drawing]

図は本考案の一実施例を示すものである。２……第１トランジスタ、６……第１コンデン
サ、１１……第２トランジスタ、１２……第２コ
ンデンサ、１４……第３トランジスタ、１５，１
６……ミユーテイング用トランジスタ。 The figure shows an embodiment of the present invention. 2...First transistor, 6...First capacitor, 11...Second transistor, 12...Second capacitor, 14...Third transistor, 15,1
6... Muting transistor.

Claims

[Claims for Utility Model Registration] A first transistor whose emitter is connected to a power supply line, a first capacitor connected between the base of the first transistor and ground, and a first transistor connected in series with the first transistor. a second transistor having the same polarity as the first transistor; a second capacitor connected between the base of the second transistor and the power supply line; a third transistor controlled by the first and second transistors; Third
and a muting transistor controlled by a transistor, and when the power supply voltage is turned on, the third transistor is driven by setting the second transistor in an off state for a predetermined time based on the charging current to the second capacitor, thereby obtaining a muting control signal, and when power is cut off, the first transistor is set to a reverse bias state by the first capacitor, thereby turning off the first transistor and driving the third transistor; A muting circuit characterized in that a muting control signal is obtained.