JPS61111057A - Image reader - Google Patents

Abstract

PURPOSE:To process the array sensor of a many-output in high speed by providing respectively a vertical signal processor to the outputs of the array sensors divided into plural numbers, reconstituting the outputs into one line after the vertical signal processing is finished and processing the horizontal signal next. CONSTITUTION:The four sets of 1st-4th CCD array photodetectors 2-5 are provided in the inside of the CCD array sensor 1, the 1st-4th charge transfer channels 6-9 are connected to photodetectors 2-5, the 1st-4th vertical signal processors 10-13 are connected to the charge transfer channels 6-9 and the output signal of the vertical signal processors 10-13 is given to shift registers 18-21. The CCD array sensor 1 is driven by a conventional method (not shown) and the electric charge stored in the photodetectors 2-5 is moved to the transfer sections 6-9 at the same time. The transfer sections 6-9 have an independent output and its output is inputted respectively to the vertical signal processors 10-13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image reading device, and particularly to an image reading device that processes output signals of a 7-ray sensor at high speed.

[Prior Art] Recently, in image reading devices, a 7-ray sensor using CCN or the like is used as a light receiving section. However, as the number of pixels increases, it becomes difficult to manufacture a CCD array that includes all pixels on one chip, and it is impossible to obtain a CCD array with the desired number of pixels without using multiple chips. I could not do it. Alternatively, a method of arranging a plurality of independent CCD arrays on a single chip and configuring them in a hybrid manner has been used. Furthermore, realizing a CCD array having a desired number of pixels by combining a plurality of CCD arrays as described above is also suitable for high-speed operation.

However, these CCD array sensors are
It has the same number of outputs as the D array, and in order to obtain a raster type image signal, it was necessary to store each output in a -H memory, convert them into serial signals, and read them out. Therefore, the raster type image signal described above has a frequency several times higher than the transfer rate of the CC lower array sensor, placing a heavy burden on subsequent signal processing means. Furthermore, if a line buffer is required for the subsequent signal processing means, a memory corresponding to the total number of pixels of the CC lower array sensor is required, which has been a bottleneck in implementing an IC.

[Objective] The object of the present invention is to solve the above drawbacks of the conventional technology, to be able to process a multi-output 7-ray sensor at high speed, and to
An object of the present invention is to provide an image reading device that can be easily converted into a C.

[Embodiment] Fig. 1 is a block diagram showing an embodiment of the present invention, and shows an example in which a CCD array sensor having four outputs, which is composed of four sets of CCD arrays on one chip, is used as an input device. .

In Fig. 1, 1 is a CCD array sensor, 2 to 5 are CCD array sensors, and 2 to 5 are CCD array sensors.
Four sets of first to fourth CCD array light receiving sections are configured inside the CD array sensor 1, and 6 to 9 are light receiving sections 2 to 4.
5, the first to fourth charge transfer channels connected to charge transfer channels 6 to 9, respectively; 10 to 13, first to fiS4 vertical signal processing devices connected to charge transfer channels 6 to 9, respectively; 18 to 21;
are shift registers that input the output signals of the vertical signal processing devices 10 to 13 to one input terminal, respectively. Also 22
is a horizontal signal processing device.

The can7 ray sensor 1 is driven in a normal manner (not shown), and the charges stored in the light receiving sections 2-5 are simultaneously transferred to the transfer sections 6-9. The transfer units 6 to 9 have independent outputs, and the outputs are sent to the vertical signal processing devices lO to 1, respectively.
3 is input.

Figure 2 shows an example of details of the vertical signal processing device, and in Figure 1,
23 is a sample hold circuit (S/H) that inputs signals from the transfer units 6 to 9 and a 7 analog-to-digital conversion circuit (A
/D) and ^/D converter.

24 is a shift register that stores the output of the ^/D converter 23 for one line of the COD light receiving section 2; 25 is a shift register that stores the output of the shift register 24 for one line;
26 is a shift register that stores the output of the shift register 25 for one line. Multipliers 27 to 29 convert the outputs of the shift registers 24 to 26 by -1 and W, respectively.
Weighted with 2J3. 30 is an adder which adds the outputs of multipliers 27 to 28 and transmits the result to the output section.
w1 to 1113 are predetermined values, which may be fixed or may be programmable by a method not shown.

Now, if wl and w3 are set to 1 and -2 is set to 2, the vertical signal processing device can perform edge emphasis processing in the vertical direction. The output of the vertical signal processing devices 10 to 13 is a shift register! 8 to 21 are input.

The shift registers 18 to 2I are each composed of two sets of shift registers each having a length equal to the number of pixels of the light receiving sections 2 to 5, and the first shift register constitutes serial in/parallel out, and the second The shift register is parallel in serial out. First, the output of the first shift register vertical signal processing device IO is input, and 1
When 947 minutes have been input, the contents of the first shift register are transferred to the second shift register using parallel out.

The outputs of shift registers 18-21 are connected to the serial output of the second shift register, and shift register 1
The output of the shift register 13 is sent to the serial input of the second shift register of the shift register 18, the output of the shift register 13 is sent to the serial input of the second shift register of the shift register 20, and the output of the shift register 20 is sent to the second shift register of the shift register 21. are connected to the serial inputs of the shift registers, respectively. Therefore, by the output of the shift register 21, the CC
One line of signals across all widths of the D-array sensor l can be read out serially. This l raster signal is input to the horizontal signal processing device 22, and edge detection is performed using a well-known method.
Edge enhancement, smoothing, etc. are performed.

By the way, the output signal rate of the horizontal signal processing device 22 is f
If l, then of course the serial outputs of shift registers 18 to 21 must be transferred at the frequency rl, but in shift registers 18 to 21, the number of pixels for one in is divided into four, so the shift-in frequency is I/4f
Therefore, the synchronization clock frequency of the vertical signal processing devices 10 to 13 (not shown) can be set to 1/4 fl.

In addition, in the above-mentioned embodiment, the vertical signal processing device l'0-1
3 was equipped with an A/D converter, but this A/D converter can also be made independent. If the A/D converters are independent, the vertical signal processing devices can be connected in cascade.

[Effects] As explained above, according to the present invention, a vertical signal processing device is provided for each output of an array sensor divided into a plurality of parts, and after vertical signal processing is completed, it is reconfigured into one line, and then horizontal signal processing is performed. (1) The speed of vertical signal processing, which is complicated, can be reduced by 1/2.
n(nli-division a).

(2) Since it is sufficient to prepare n vertical signal processing devices with the same configuration, it is suitable for IC implementation.

(3) The internal line memory of each vertical signal processing device can be reduced.

(4) Any number of vertical signal processing devices can be connected in cascade.

Effects such as this can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a vertical signal processing device. l...4-divided CCn array sensor, +0.11
, 12.13... Vertical signal processing device. 18.19, 20.21...Shift register, 22.
...Horizontal signal processing device, 23...A/D converter, 24.25.28...Line buffer, 27.28.
29... Multiplier, 30... Adder. τ Figure 1

Claims (1)

[Scope of Claims] An array sensor in which one line is composed of a plurality of elements and signals are simultaneously output from each element; and a plurality of shift registers that reconfigure the outputs of the array sensor into one line; An image reading device comprising: a processing device disposed between an array sensor and the shift register for calculating a signal between at least a front line or a rear line.