JPS61109145U - - Google Patents
Info
- Publication number
- JPS61109145U JPS61109145U JP19291884U JP19291884U JPS61109145U JP S61109145 U JPS61109145 U JP S61109145U JP 19291884 U JP19291884 U JP 19291884U JP 19291884 U JP19291884 U JP 19291884U JP S61109145 U JPS61109145 U JP S61109145U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor
- mold
- frame
- outer frames
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案リードフレームの一実施例を示
す平面図、第2図は同じくモールド型へのリード
フレーム配列図、第3図は同じく残部樹脂の突落
し説明図、第4図は従来のリードフレームを示す
平面図、第5図は同じくモールド型へのリードフ
レーム配列図、第6図は同じくモールド成形品の
側面図、第7図は同じくゲート部の分離説明図、
第8図は同じくモールド工程後の送り状態を示す
図である。
1……リードフレーム、1a……外枠、2……
パツケージ、3ゲート部、4,5……インデツク
ス表示、9,9′……切欠部、10……突落し棒
。
Fig. 1 is a plan view showing an embodiment of the lead frame of the present invention, Fig. 2 is a diagram of the arrangement of the lead frame in a mold, Fig. 3 is an explanatory diagram of the falling of the remaining resin, and Fig. 4 is a diagram of the conventional lead frame. FIG. 5 is a plan view showing the lead frame, FIG. 5 is a lead frame arrangement diagram in the mold, FIG. 6 is a side view of the molded product, FIG. 7 is a separate explanatory diagram of the gate part,
FIG. 8 is a diagram showing the feeding state after the molding process. 1... Lead frame, 1a... Outer frame, 2...
Package, 3 gate portion, 4, 5...index display, 9,9'...notch portion, 10...falling rod.
Claims (1)
に支持されるリード部とを有する半導体用のリー
ドフレームにおいて、モールド型のゲート部に対
応する位置と、その反対側の対称位置にそれぞれ
樹脂残部を突き落すための切欠部を前記外枠に設
けたことを特徴とする半導体用リードフレ―ム。 In a semiconductor lead frame having two outer frames extending substantially in parallel and a lead part supported by the outer frames, a position corresponding to the gate part of the mold mold and a symmetrical position on the opposite side thereof. A lead frame for a semiconductor, characterized in that the outer frame is provided with a notch for pushing out the remaining resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19291884U JPS61109145U (en) | 1984-12-21 | 1984-12-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19291884U JPS61109145U (en) | 1984-12-21 | 1984-12-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61109145U true JPS61109145U (en) | 1986-07-10 |
Family
ID=30750331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19291884U Pending JPS61109145U (en) | 1984-12-21 | 1984-12-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61109145U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206353A (en) * | 1992-05-27 | 1993-08-13 | Apitsuku Yamada Kk | Degate method for lead frame and lead frame used therefor |
-
1984
- 1984-12-21 JP JP19291884U patent/JPS61109145U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206353A (en) * | 1992-05-27 | 1993-08-13 | Apitsuku Yamada Kk | Degate method for lead frame and lead frame used therefor |
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