JPS61107230U - - Google Patents
Info
- Publication number
- JPS61107230U JPS61107230U JP19077984U JP19077984U JPS61107230U JP S61107230 U JPS61107230 U JP S61107230U JP 19077984 U JP19077984 U JP 19077984U JP 19077984 U JP19077984 U JP 19077984U JP S61107230 U JPS61107230 U JP S61107230U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- current source
- tuning
- source circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は本考案に係る周波数制御電圧の重畳回
路を示す回路図、第２図は本考案回路の具体的一
例を示す回路図、第３図は本考案により補正され
る重畳利得特性を示す特性図、第４図は同上特性
を理想特性と比較するための特性図、第５図は従
来の周波数制御電圧の重畳回路の一例を示す回路
図、第６図は第５図の１チヤンネル分に相当する
等価回路を示す回路図、第７図は同調電圧の感度
特性を示す特性図、第８図は従来の周波数制御電
圧の重畳利得特性を示す特性図である。
１……電子同調チユーナ、２……電圧入力端子
、３……重畳抵抗、４……周波数制御電圧源、５
……重畳抵抗、２１……可変抵抗器、２１１……
摺動端、２２……抵抗、２３……電流源回路、２
４……トランジスタ、２５〜２７……抵抗。
Figure 1 is a circuit diagram showing a frequency control voltage superimposition circuit according to the present invention, Figure 2 is a circuit diagram showing a specific example of the circuit of the present invention, and Figure 3 is a diagram showing the superposition gain characteristic corrected by the present invention. Figure 4 is a characteristic diagram for comparing the above characteristics with ideal characteristics, Figure 5 is a circuit diagram showing an example of a conventional frequency control voltage superimposition circuit, and Figure 6 is a diagram for one channel of Figure 5. FIG. 7 is a characteristic diagram showing the sensitivity characteristic of the tuning voltage, and FIG. 8 is a characteristic diagram showing the superimposed gain characteristic of the conventional frequency control voltage. 1...Electronic tuning tuner, 2...Voltage input terminal, 3...Superimposition resistor, 4...Frequency control voltage source, 5
...Superimposed resistor, 21...Variable resistor, 21 1 ...
Sliding end, 22...Resistor, 23...Current source circuit, 2
4...Transistor, 25-27...Resistor.
Claims (1)
て印加される電圧入力端子を有するチユーナと、 電圧源からの電圧が一端に供給され、他端に分
圧手段が接続された第１の抵抗を含み、その分圧
手段によつて分圧した電圧を同調電圧とする電圧
設定手段と、 前記電圧源と基準電位点との間に接続された電
流源回路と、 前記分圧手段にて分圧した電圧値に応じて前記
電流源回路の出力電流が変化するように、前記電
圧設定手段の設定電圧を電流源回路に加える手段
とを具備し、 同調電圧に対する前記制御電圧の重畳利得に変
化を与えるようにしたことを特徴とする周波数制
御電圧の重畳回路。[Claims for Utility Model Registration] A tuner having a voltage input terminal to which a tuning voltage and a control voltage for frequency fine tuning are applied in a superimposed manner, and a voltage dividing means to which voltage from a voltage source is supplied to one end and to the other end. a voltage setting means that includes a first resistor connected to the first resistor and uses the voltage divided by the voltage dividing means as a tuning voltage; and a current source circuit connected between the voltage source and a reference potential point. , means for applying the set voltage of the voltage setting means to the current source circuit so that the output current of the current source circuit changes according to the voltage value divided by the voltage dividing means, A frequency control voltage superimposition circuit characterized in that the superposition gain of the control voltage is varied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19077984U JPS61107230U (en) | 1984-12-18 | 1984-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19077984U JPS61107230U (en) | 1984-12-18 | 1984-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107230U true JPS61107230U (en) | 1986-07-08 |
Family
ID=30748230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19077984U Pending JPS61107230U (en) | 1984-12-18 | 1984-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107230U (en) |
-
1984
- 1984-12-18 JP JP19077984U patent/JPS61107230U/ja active Pending
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