JPS61106039U - - Google Patents

Info

Publication number
JPS61106039U
JPS61106039U JP19159984U JP19159984U JPS61106039U JP S61106039 U JPS61106039 U JP S61106039U JP 19159984 U JP19159984 U JP 19159984U JP 19159984 U JP19159984 U JP 19159984U JP S61106039 U JPS61106039 U JP S61106039U
Authority
JP
Japan
Prior art keywords
semiconductor device
view
type semiconductor
pitch
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19159984U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19159984U priority Critical patent/JPS61106039U/ja
Publication of JPS61106039U publication Critical patent/JPS61106039U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図イ〜ハは本考案のDIZP型半導体装置
を示し、第1図イは平面図、第1図ロは側面図で
あり、第1図ハはこの半導体装置をプリント基板
へ塔載した場合の配線パターンを示す平面図であ
る。第2図イ〜ハは従来のDIP型半導体装置を
示し、第2図イは平面図、第2図ロは側面図、第
2図ハはこの半導体装置をプリント基板へ塔載し
た場合の配線パターンを示す平面図である。 主な図番の説明、1は半導体装置本体、2はリ
ードピン、3はVccライン、4はGNDライン
である。
Figures 1A to 1C show the DIZP type semiconductor device of the present invention, Figure 1A is a plan view, Figure 1B is a side view, and Figure 1C is a diagram showing this semiconductor device mounted on a printed circuit board. FIG. 3 is a plan view showing a wiring pattern in this case. Figures 2A to 2C show a conventional DIP type semiconductor device, Figure 2A is a plan view, Figure 2B is a side view, and Figure 2C is wiring when this semiconductor device is mounted on a printed circuit board. FIG. 3 is a plan view showing a pattern. Explanation of the main figure numbers: 1 is the semiconductor device body, 2 is the lead pin, 3 is the Vcc line, and 4 is the GND line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] DIP型半導体装置において、対向する一方の
リードピンが他方のリードピンと半ピツチずれた
位置に配置されたことを特徴とするDIP型半導
体装置。
1. A DIP type semiconductor device, wherein one of the opposing lead pins is disposed at a position shifted by half a pitch from the other lead pin.
JP19159984U 1984-12-18 1984-12-18 Pending JPS61106039U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19159984U JPS61106039U (en) 1984-12-18 1984-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19159984U JPS61106039U (en) 1984-12-18 1984-12-18

Publications (1)

Publication Number Publication Date
JPS61106039U true JPS61106039U (en) 1986-07-05

Family

ID=30749038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19159984U Pending JPS61106039U (en) 1984-12-18 1984-12-18

Country Status (1)

Country Link
JP (1) JPS61106039U (en)

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