JPS611052A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the withstand of the junction of an emitter region and a base region by forming the portion adjacent to the bonding end of the emitter and base regions terminated on the surface of a semiconductor layer of the base region in a low impurity density. CONSTITUTION:An n<+> type buried layer 2 is formed in a p type Si substrate 1, and n type epitaxial layer 3 is formed on the substrate 1. Then, a p type base region 5 and a p<+> type graft base region 6 are formed in the layer 3. Then, an n type impurity such as As is implanted to the surface of the layer 3 through a thin SiO2 film 11 formed on the surface of the layer 3, and heat treated. Then, after the film 11 is removed, an SiO2 film 7 and As-doped polycrystalline Si film 8 are formed in the layer 3, heat treated to form an n<+> type emitter region 9. In an npn type bipolar transistor formed in this manner, the impurity density of the portion adjacent to the surface of the layer 3 of the region 5 decreases. Thus, the reverse withstand in the bonding end 14a of the emitter and base junction 14 can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a first conductor formed in a semiconductor substrate! The present invention relates to a semiconductor device including a mold base region and a second conductivity type emitter region formed in the first conductivity type base region, and a method for manufacturing the same.

BACKGROUND TECHNOLOGY AND SEVEN PROBLEMS In order to improve the performance of bipolar LSIs, not only the planar dimensions but also the vertical (depth direction) dimensions of bipolar transistors as elements constituting the LSI have been changed. There is. As a result, the junction between the base region and the emitter region becomes shallower, so that the surface impurity concentration in the base region and the emitter region increases and the impurity concentration distribution also becomes steeper.

By the way, bipolar transistors as elements constituting bipolar L and SI have conventionally been manufactured by, for example, the following method. That is, as shown in FIG. 1A,
First, an n+ type buried layer 2 is formed on a p-type silicon substrate 1,
Next, an n-type epitaxial growth layer 3 is formed on the p-type silicon substrate 1.

Next, a p-type base region 5 and a p-type craft base region 6 connected to the base region 5 are formed in this epitaxial growth layer 3. Next, as shown in Figure 1B,
For example, 5i is deposited on the epitaxial growth layer 3 by the OVD method.
An N2 film 7 is deposited and then a predetermined portion of this SiO2 film 7 is etched away to form an open lower a. Next, the OVD method (for example, arsenic As T, y high α degree 1
A doped polycrystalline silicon film is deposited on the entire surface, and then a predetermined portion of the polycrystalline silicon film is etched away to form a polycrystalline silicon film 8 having a predetermined shape, and then a predetermined heat treatment (emitter diffusion) is performed. By doing this, As in the polycrystalline silicon film 8 is removed from the epitaxially grown layer 3.
A type 1 emitter region 9 is formed by diffusion.

Note that the epitaxial growth layer 31 existing between the base region 5 and the buried layer 2 constitutes an n-type collector region 10. After this, emitter region 9, base region 5
and an electrode (not shown) for the collector region 10, respectively, to complete an npn type bibor 2 transistor.

FIG. 2 shows the impurity concentration distribution between arrows A and B in the conventional npn type bipolar transistor shown in FIG. As is clear from FIG. 2, the impurity concentration in the direction of the arrow in the base region 5 reaches its maximum value at the entrance surface of the epitaxial growth layer 3, and increases as the depth increases. The distribution is such that it decreases to . The impurity concentration in the direction indicated by the arrow in the base region 5 is, for example, when the junction depth Xjb of the base region 5 is set to about 0.2 μm or less, the impurity concentration at the optical surface of the base region 5 is, for example, 1019α″3 or more. At the same time, as the depths become smaller, FJI! This results in an extremely steep impurity concentration segment where the degree of controversy decreases rapidly. By the way, the emitter region
The reverse breakdown voltage of the junction (ICE junction) between the □ region 9 and the base region 5 becomes lower as the degree of impurity wlJa of the base region 5 is adjusted. Therefore, the reverse breakdown voltage of the EB junction is
The reverse breakdown voltage of the EB junction is determined by the reverse breakdown voltage at the junction end where the impurity concentration is highest, so for example, if the junction of the base region 5 is made shallow as described above, the reverse breakdown voltage of the EB junction will decrease. There was a problem. Note that if the impurity concentration of the base region 5 is iQ18cm-3 or more,
It is known that Zener destruction is dominant in the reverse characteristics of a BB junction.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which corrects the above-mentioned drawbacks of conventional bipolar transistors.

Summary of the Invention A semiconductor device according to the present invention includes a base region of a first conductivity type formed in a semiconductor base layer, and an emitter region of a second conductivity type formed in the base region of the first conductivity type. In the semiconductor device, a portion of the base region adjacent to a junction end between the emitter region and the base region, which terminates on the surface of the semiconductor base layer, has a low impurity concentration. With this configuration, the breakdown voltage of the junction between the emitter region and the base region can be made higher than in the prior art.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that a base region of a first conductivity type formed in a semiconductor base layer and a base region of a second conductivity type formed in the base region of the first conductivity type are formed in the semiconductor base layer. In the method of manufacturing a semiconductor device, the portion of the base region adjacent to the junction end of the emitter region and the base region, which terminates on the surface of the semiconductor base layer, has a second conductivity type. By introducing impurities, the portion of the base region adjacent to the junction end has a low impurity concentration.By doing this, the breakdown voltage of the junction between the emitter region and the base region is lower than that of the conventional method. Therefore, it is possible to manufacture a high-quality semiconductor device R.

Examples Below, a semiconductor device and a method for manufacturing the same according to the present invention will be described as an LSI.
An embodiment applied to the manufacture of an npn type bipolar transistor constituting the present invention will be described with reference to the drawings.

Note that in FIGS. 3A and 3B, the same parts as in FIGS. 1A and 1B are designated by the same reference numerals, and the explanation thereof will be omitted as necessary.

As shown in FIG. 3A, first, an n+ buried layer 2 is formed on a p-type silicon substrate 1 in the same manner as in FIG. 1A, and then an n-type epitaxial growth layer 3 is formed on the p-type silicon substrate 1. , a p-type base region 5 and a p+-type graft base region 6 are formed in this epitaxial growth layer 3. The base region 5 is formed by forming a thin SiO2 film 11 with a thickness of, for example, 150A on the surface of the epitaxial growth layer 3, and then depositing this SiO2 film 11 into the epitaxial growth layer 3 under conditions of, for example, an acceleration energy of 3QKeV and a dose of 1X10146In-2. It was formed by selectively ion-implanting BF2.

Next, the surface of the epitaxial growth layer 3 is again coated with TnW non-Ni via the SiO2 film 11 at an acceleration energy of 3QKeV and a dose of i-2810" cIn-20).
? I, Example 1f I As is ion-implanted (As in the epitaxial growth layer 3 is represented by .). After this, for example, N2
By performing heat treatment in an atmosphere for 7500.30 minutes, damage to the epitaxial growth layer 3 caused by ion implantation is recovered, and B in the base region 5 is electrically activated.

Next, after removing the 8iQ2 film 11, as shown in FIG. 3B, a 5i02 film 7 having a thickness of 3000λ, for example, is placed on the epitaxial growth layer 3, as shown in FIG. 1B.
For example, after forming an AS-doped polycrystalline silicon film 8 with a film thickness of 500X, heat treatment (emitter diffusion) is performed at 950C for 15 minutes in an N2 atmosphere.
By doing this, As in the polycrystalline silicon film 8 is diffused into the epitaxial growth layer 3 to form an n-type emitter region 9. Note that, as in the conventional case, the collector region 10 is constituted by the epitaxial growth layer 3I existing between the base region 5 and the buried layer 2. Thereafter, electrodes for the emitter region 9, base region 5, and collector region 10 are formed to complete a desired npn type bipolar transistor.

FIG. 4 shows the impurity concentration distribution in the direction of arrow C1D in the npn type bipolar transistor shown in FIG. 3B manufactured according to the above embodiment, with the surface of epitaxial growth layer 3 as the origin. Note that this figure 4 shows the third figure for comparison.
The same impurity concentration distribution as described above is also shown when no ion implantation is performed in the process shown in Figure A. As is clear from FIG. 4, the surface impurity concentration 051 of the base region 5 is approximately 8×10 18 cIIL compared to the surface impurity concentration 082 when M ion implantation is not performed.
-3 lower. Furthermore, the impurity concentration in the portion of the base region 5 adjacent to the surface of the epitaxially grown layer 3 is considerably lower than in the case where no ion implantation was performed.
It can be seen that there is a peak of impurity concentration at a depth of approximately 0.03 μm. The reason why the impurity concentration distribution in the direction of arrow C in the base region 5 becomes like this is because the BC p-type impurity in the base region 5 and the compensation stone are caused by As (n-type impurity) ion-implanted into the surface of the epitaxial growth layer 3. This is because of this. As a result, the EB junction 14 (third
Since the impurity concentration of the portion 5a adjacent to the junction end 14a of the EB junction 14 (see figure B) is lower, the junction end 14a of the EB junction 14
The reverse breakdown voltage can be made easier than in the past by the reduction in impurity concentration. Therefore, as shown in FIG. 4, the junction of the base region 5 is
Even when shallowed to about m, there is almost no reduction in the reverse breakdown voltage of the EB junction.

Further, according to the above embodiment, as is clear from FIG. 4, the impurity v concentration distribution in the portion 5b of the base region 5 located below the emitter region 9 (so-called 1ntrinsic base region) is almost changed. Without base area 5
The surface impurity concentration can be reduced.

Further, according to the above-described embodiment, the base region 5 is formed by implanting & in the step shown in FIG.
Since the surface impurity concentration is reduced, the manufacturing process is simple, and the surface impurity concentration can be reduced accurately and reliably.

The present invention is not limited to the above-mentioned embodiments, but may be freely modified based on the technical idea of the present invention. For example, the conditions such as the acceleration energy and dose amount of the 7tAS ion implantation performed in the process shown in FIG. However, if the peak concentration in the impurity concentration distribution in the direction of arrow C in Figure 3B shown in Figure 4 is larger than 7x1Q18crn-3, the reverse leakage current of nB junction 14 (1 (reverse bias of B junction 14) For example, the value of 3.5 V) becomes larger than that in the forward direction, which is not preferable, so it is preferable that the conditions for the ion implantation are selected so that the peak concentration is 7 X I Q 18 (@-5 or less). The above fruit [I here, M
M ions are implanted over the entire surface of the epitaxial growth layer 3, or M ions are selectively implanted into a portion of the base region 5 adjacent to the junction end 14a of the BB junction 14, but is not limited to this. For example, the region where M is implanted can be changed as appropriate. In the above embodiment, A is used as an impurity to reduce the surface impurity concentration of the base region 5.
Alternatively, other types of impurities may be used as long as they have a conductivity type opposite to that of the impurities constituting the base region 5 and have a relatively small diffusion coefficient.

Effects of the Invention According to the semiconductor device of the present invention, since the adjacent portion of the base region at the junction end f between the emitter region and the base region which terminates on the surface of the semiconductor base layer has a low impurity concentration, the emitter region and The breakdown voltage of the junction with the base region can be increased compared to the conventional method.

Further, according to the method for manufacturing a semiconductor device according to the present invention, the first
A second conductivity type impurity is introduced into a portion of the conductivity type base region adjacent to the junction end between the emitter region and the base region which terminates on the surface of the semiconductor base layer. Therefore, it is possible to manufacture a semiconductor device in which the breakdown voltage of the junction between the emitter region and the base region is higher than that of the conventional method.

[Brief explanation of the drawing]

First, Figures 1 and 1B are cross-sectional views showing steps J@t of an example of a conventional method for manufacturing an npn-type bipolar transistor.
FIG. 2 is a graph showing the impurity concentration distribution in the direction of arrow A%B in the conventional npn bipolar transistor shown in FIG. 1B, with the surface of the epitaxial growth layer as the origin, and FIGS. 3A and 3B are the semiconductor devices according to the present invention. FIG. 4 is a cross-sectional view showing the process order of an embodiment in which the manufacturing method is applied to the manufacturing of an npn-type bipolar transistor, and FIG. 2 is a graph similar to FIG. 2 showing the impurity concentration distribution of FIG. 2 with the bottom surface of the epitaxial growth layer 3 as the origin. In addition, in the symbols used in the drawings, 3 ・・・・・・・・・・・・ Epitaxial growth layer (semiconductor base layer) 5 ・・・・・・・・・・・・・・・
・Base area 6 ・・・・・・・・・・・・・・・ Graft base area 8 ・・・・・・・・・・・・・・・
Polycrystalline silicon film 9・・・・・・・・・・・・・・・
Emitter region 10・・・・・・・・・・・・ Collector area 14・・・・・・・・・・・・ 14
B junction 14a......This is a joint end.

Claims (1)

[Claims] 1. A base region of a first conductivity type formed in a semiconductor base layer and an emitter region of a second conductivity type formed in the base region of the first conductivity type. A semiconductor device characterized in that a portion of the base region adjacent to a junction end between the emitter region and the base region that terminates on the surface of the semiconductor base layer has a low impurity concentration. 2. A method for manufacturing a semiconductor device comprising a base region of a first conductivity type formed in a semiconductor base layer and an emitter region of a second conductivity type formed in the base region of the first conductivity type. In the above base area,
A second conductivity type impurity is introduced into a portion adjacent to the junction end of the emitter region and the base region that terminates on the surface of the semiconductor base layer, whereby the portion of the base region adjacent to the junction end is doped with a low impurity concentration. A method of manufacturing a semiconductor device, characterized in that: