JPS61104493A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device that can be actuated in a cycle time which satisfies sufficiently the access time proper to a dynamic RAM, by providing two divided groups of dynamic and static RAMs and actuating both groups alternately to each other. CONSTITUTION:A memory block 1 consisting of DRAM1A-1H and a memory block 2 consisting of DRAM2A-2H fix row addresses for a fixed period in a page mode. Meanwhile plural column addresses are written or read. In this case, the column address strobe signal -CAS which is used for the extraction of the column address into the DRAM has phases opposite to each other be tween blocks 1 and 2. Then the addresses are set alternately to each other between both blocks. Furthermore SRAM21 and 22 are added to blocks 1 and 2. These SRAMs are driven while the -RAS is reset to an inactive mode. Thus the writing or reading of data is not interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention is applicable to, for example, a 256-bit dynamic RA.
The present invention relates to a video memory device suitable for constructing a frame memory using M.

[Conventional technology]

The frame memory conventionally consisted of 64 64-bit dynamic RAMs.

For example, if the sampling period of the digital video signal is 70
At the time of N5EC, it was not possible to write and read digital video signals in real time due to the access time constraints of the dynamic RAM, and therefore the input digital video signal was parallelized for each plurality of sample data.

However, due to advances in semiconductor technology, recently 25
Six-bit dynamic RAM is becoming relatively easy to obtain. However, the access time is still insufficient, and it is necessary to perform parallelization processing at the time of writing and serialization processing at the time of reading.

[Problem that the invention seeks to solve]

When a large number of dynamic RAMs are used in the past, and input digital video signals are written in parallel and read out in serial, the scale of the hardware becomes large.
This has the disadvantage that timing control becomes troublesome and furthermore, it becomes difficult to check the circuit.

For example, this invention provides a 256-bit dynamic RA.
An object of the present invention is to provide a memory device capable of writing one frame of 14 MHz video information in real time using M (sampling rate) and as serial data.

[Means for solving problems]

The memory device of the present invention includes dynamic RAM (IA~2H, 2A~2H) divided into two groups, static RAM (21, 22), and address means (11°12.20) for supplying addresses to each RAM. ) and
In order to operate the dynamic RAM of each group in the page mode alternately, the row address strobe signal RAS is activated at a predetermined period, and during this period, the column address strobe signal CAS with the opposite phase is supplied to each group to alternate the groups. While the row address strobe signal RAS is inactive, the static RAM
It is configured to perform address settings for.

[Effect]

Since the two groups are operated alternately, they can be operated with a cycle time that fully satisfies the access time inherent in dynamic RAM. Furthermore, even if the RAS pulse width in one page mode is limited, writing or reading continuity can be maintained by activating the static RAM each time the RAS is returned to inactive.

〔Example〕

An embodiment in which the present invention is applied to a frame memory will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a frame memory to which the present invention is applied.

In FIG. 1, 1 and 2 indicate memory blocks, respectively. One memory block 1 is eight 256-bit dynamic RAMIAs.

It is composed of IB, IC, ID, IE, IF, IG, and IH, and the other memory block 2 is also composed of eight 256
It is composed of dynamic RAMs 2A to 2H of bits.

Memory block 1.2 is operated in page mode for writing/continue reading. In this page mode, a row address is fixed for a certain period of time, and a plurality of column addresses are changed during that period to perform writing or reading. At this time, the column address is
The column address strobe signal CA″S for loading into memory blocks 1 and 2 is reversed in phase, and addresses are set alternately in the blocks.
Video information digitized at a sampling rate of Hz (70n5ec) is written to the memory block 1.2 in alternating data. As a result, the operation cycle of the DRAM of each block is set to 140 nsec, which is twice the sampling period, and satisfies the minimum access time of 12 (lnsec) of the DRAM used in the embodiment. Therefore, according to this configuration, the sampling rate is 14.
It becomes possible to write and read 3 MHz video data to and from memory in real time.

However, when a DRAM is used in page mode, it is necessary to keep the row address strobe signal RAS active (low level) for a certain period of time in order to fix the row address for a certain period of time. The maximum time width that this RAS can be kept active, that is, the RAS pulse width t, has an upper limit inherent to D-quality AM elements, for example, the one used in the example must be within 10 μSaC. . However, when storing video information, the data is continuous for at least 50 μsec (one line), so if you return RAS to inactive every 10 μsec (or less) in page mode, it will be difficult to write continuous data. Become.

Therefore, as shown in Figure 1, static RAM (SRA)
M) Add 21.22 to each block 1, 2 and RAS
These SRAMs are driven while the SRAM is returning to inactive state so that writing, reading, or reading of data is not interrupted.

In FIG. 1, 3 is an input terminal to which, for example, a still image color video signal for one frame is supplied. This input color video signal is passed through a low-pass filter 4 to the A/D
It is supplied to converter 5.

A/D converter 5 has 4 fsc = 14.3M H
z (fsc is the color subcarrier frequency) is used as the sampling frequency, a digital color video signal of 8 bits per sample is generated, and this digital color video signal is sent to the memory blocks 1 and 2 and the SRAM 21.22.
supplied to

11 indicates an address counter that generates a 9-bit column address, and 12 indicates a 9-bit row (column) address.
row) indicates the address counter that generates the address.

The outputs of these address counters 11 and 12 are supplied to an address selector 16.

Dynamic RAMIA to IH of memory block 1 and dynamic RAM 2A to 2H of memory block 2
are commonly supplied with a column address or a row address via an address selector 16.

The row address and column address on the same address bus are individually taken into the address decoder in each RAM by a row address strobe signal RAS and a column address strobe signal CAS.

Note that the address counter 11 is supplied with a sampling clock SC synchronized with the input still image color video signal as a clock input, and also supplied with a horizontal synchronization pulse 100 as a clear pulse.

The address counter 12 is supplied with a horizontal synchronizing pulse (2) as a clock input and a vertical synchronizing pulse (V) as a clear pulse. In other words, dynamic R
The row addresses (0 to 511) of AMIA to LH and 2A to 2H are used as line addresses, and these (0 to 511)
The column address of is taken as the sample address within the line.

When an NTSC color video signal is sampled at a frequency of 4 fsc, one frame has 525 lines, and each line includes 910 samples. but,
Valid data in one frame fits within 512 lines.

FIG. 2 is a time chart showing an outline of page mode write/success operation.

FIG. 2A shows a horizontal synchronization pulse synchronized with the digital color video signal from the A/D converter 5. This horizontal synchronization pulse 100 is supplied to the address counter 12, and
A row address that changes every horizontal period is generated, and the gate circuit 20 generates a row address strobe signal RAS shown in FIG. 2. In addition, row address strobe signal R
From AS, address selector 1 is connected via gate plane path 20.
A control signal shown in FIG. As shown in FIG. 2F, in the illustrated example, the row address is set to 0.

The address counter 11 is cleared by the horizontal synchronization pulse ■, and when this cleared state is released, the address counter 11 starts counting operation by the sampling clock SC, and the column address increments as shown in FIG. 2F. .

A column address strobe signal CAS1 shown in the second diagram is generated from the least significant bit of this column address by the gate circuit 20 and supplied to the memory block 1. Further, in the gate circuit 20, a column address strobe signal CAS2 of opposite phase shown in FIG. 2 is formed and supplied to the memory block 2. This causes memory blocks 1 and 2 to be addressed alternately in sampling periods.

As a result, when the first sample data of one horizontal period is written to the dynamic RAMs IH of the memory block 1, the next sample data is written to the dynamic RAMs 2A to 2H of the memory block 2. When this operation is repeated and the next horizontal synchronizing pulse H is supplied, the address counter 11 is cleared, the column address returns to its initial value, and the row address is incremented by +1.

The column address of a 256-bit dynamic RAM is:
(0 to 511), and therefore, a maximum of 1024 pieces of input sample data shown in FIG. 2G can be written within one horizontal period.

In the page mode, the row address strobe signal RAS is deactivated (“
1"), it will not be screwed.

Therefore, as shown in Figure 3, RAS is set to 8 within the IH period.
RAS pulse width t RAS in page mode once (every 114 samplings) is 7.94μse
c. Then, in the period when RAS is inactive (1''), the static RAM 21.
A write enable WEI and 2 (out enable 100 when reading) are sent to 22 to activate the SRAM and prevent writing from being interrupted.

Address SAD given to static RAM21.22
is formed by the upper three bits of the column address counter 11 and all nine bits of the row address counter 12.

To explain the details with reference to the time chart of FIG. 4, in each horizontal interval, the column address specification (114th sample) in the previous page mode for the first memory block 1 is completed, and the column address strobe signal CASI is activated. When it rises, the row address strobe signal RASI is set to 1''.
, and after two sample intervals have passed, RASI is activated (“0”) to start the next page mode. The period in which RAS 1 is “1” is 140 μsec,
This satisfies the minimum precharge time t□ required for the DRAM used in the embodiment. The write enable WE for the static RAM 21 (out enable when reading is 101) becomes active (“0”) at an odd sample point (115th sample) in the latter half of the interval where RAS1 is “1” as shown in FIG. This causes the 115th sample data to be written into the SRAM 21. In the next page mode, after RAS 1 falls, CASI falls every odd sample, and writing to dynamic RASIA to IH is performed.

In the second memory block 2, when CAS2 rises at the end of addressing the 114th sample, RAS2
returns to inactive ("1')" and after the -12 sample period has elapsed, RAS2 becomes active ("0") and the next page mode begins.

Write enable WE for static RAM22
2 (out enable 0E2 when reading) is RAS
2 is an even sample point in the latter half of the inactive interval (the first
16 samples) and active (“O”) as shown in Figure 4.
Falling down. As a result, the 116th end pull data is written into the SRAM2.

In the next page mode, after RAS 2 falls, every even sample (in reverse phase with memory block 2)
AS2 falls and writing to the dynamic RAMs 2A to 2H is performed.

In this way, the DRAM and SRAM of memory blocks 1 and 2 are used alternately to write data, thereby enabling real-time processing.

The digital color video signals read out from the memory blocks 1 and 2 are supplied to the latch 6, and the output inputs of the memory blocks 1 and 2 are connected to the control signal (
D/
The signal is supplied to the A converter 8, converted into an analog signal, and taken out to the output terminal 10 via the low-pass filter 9.

Address control for each block 1.2 is the same as for writing.

Note that the static RAM used in the above embodiment requires a capacity of 8 times x 512 lines = 4096 bytes when RAS falls 8 times in 1 line. Furthermore, RAS
If the pulse width t RAS is within 10μsec, IH
It is sufficient to return RAS to "1" at least six times in the section.

〔Effect of the invention〕

As described above, the present invention uses two groups of dynamic RAM alternately in page mode to substantially double the operating cycle time, so that the sampling rate can be increased to 14.
．． Even 3MHz (4fsc) digital video data can be written and read in real time.

In addition, even if the time width in which RAS can be activated in page mode is limited, RAS is deactivated at a predetermined period and static RAM is activated during that period, so continuous data writing without data loss is possible. Reading becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a frame memory device showing an embodiment of the present invention, and FIGS. 2 to 4 are time charts showing the operation of the frame memory device of FIG. In addition, in the symbols used in the drawings, 1.2-・--
-Memory block 11.12...-Address counter 20--Gate circuit 21.22-
They are static RAM IA to IH-, dynamic RAM 2A to 2H-, and dynamic RAM.

Claims (1)

[Claims] It is equipped with a dynamic RAM divided into two groups, a static RAM, and an address means for supplying an address to each RAM, and in order to operate the dynamic RAM of each group in a page mode alternately, a row address strobe signal is provided. @RAS@ is activated at a predetermined period, and during that period, column address strobe signals @CAS@ with mutually opposite phases are supplied to each group to set alternate addresses for the groups, and when the row address strobe signal @RAS@ is inactive. A memory device in which addresses are set for the static RAM.