JPS6110386A - Extrapolation arithmetic circuit for digital convergence device - Google Patents

Abstract

PURPOSE:To prevent the output of an abnormal correcting value by inhibiting an input of an arithmetic output to an adder when a subtractor is in borrow state, and bringing the output of the adder to a high level in overflow state. CONSTITUTION:When subtractors 9f, 9h are in borrow state, input inhibition circuits 9n, 9p are activated by the output of borrow detection circuits 9l, 9m and an output from the subtractors 9f, 9h is not inputted to adders 9g, 9i. When the adders 9g, 9i are in overflow state, the output of the overflow detection circuits 9q, 9r activates the high level output circuits 9s, 9t and the output of the adders 9g, 9i is brought all into high level. Thus, the output of the extrapolarion operating circuit is controlled so as to prevent an abnormal convergence correction current from flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an extrapolation circuit for a digital convergence device.

[Prior art]

18th! ff is a block diagram of a known digital convergence device, in which 1 is a test pattern generation circuit, 2 is a control panel, 3 is a write address generation circuit, and 4 is a block diagram of a known digital convergence device.
is a multiplexer, 5 is a write address generation circuit, 6 is a field memory, 7 is a read address generation circuit, 8 is a read/write control circuit, 9 is a horizontal extrapolation calculation circuit, 10
is a line memory, 11 is a vertical extrapolation calculation circuit, 12 is a vertical interpolation calculation circuit, and 13 is DAfl! L#! 14 is a low-pass filter, 15 is a current amplification circuit, and 16 is a convergence coil.

Further, although not shown in the figure, an actual convergence device requires a total of four correction circuits, each of which performs correction in the radial direction for red, green, and blue, and correction in the lateral direction for blue.

FIG. 2 shows a detailed configuration diagram of the horizontal extrapolation calculation circuit 9. 9
a, 9b, 9c, 9d, and 9e are the 1st and 2nd degrees, respectively. Third.
4th. 5th shift register, 9f is the first subtracter, 9g is the first adder, 9h is the second subtracter, 91 is the second adder, 9
j is a gate circuit, and 9 is a timing pulse generation circuit. 3 is a timing diagram of FIG. 2, and FIG. 4 is a conceptual diagram of FIG. 2.

Next, the operation will be explained. The digital convergence device shown in FIG. 1 is well known and is not particularly important with respect to the present invention, so a description thereof will be omitted.

The conceptual diagram of FIG. 4 explains the operation of the horizontal extrapolation calculation circuit 9 of FIG. Figure 4 tal shows the crosshatch signal for convergence adjustment projected on the screen,
The surrounding points P are adjustment points determined by the calculation of the horizontal extrapolation calculation circuit 9.

FIG. 4(b) shows the convergence correction current of any one line on the screen, and 31 to a9 in the figure are the positions adjusted by operating the control panel 2 in FIG. 1 while looking at the screen, and aO and alo are adjustment points determined by the horizontal extrapolation calculation circuit 9.

The value of aO is a□= (al-a2)+a1 =2a1-a2a
The value of 10 is obtained as a digital calculation value expressed as a1o=<as-as)+a9=2a9-ae.

FIG. 3 is a diagram showing the timing of each part in FIG. 2. FIG. 3 (al is the input to the Lujistar 9a, FIG. 3(b),
+C), ldl, fed, and ifl are the respective registers 9a and 9b.

Outputs of 9c, 9d, and 9a, Fig. 3 (phantom is gate circuit 9j
The output of FIG. 3+h) indicates the time. Data is transferred pin by pin to each register using clock pulses synchronized with an integral multiple of the television scanning speed.

Time t5. During periods excluding t6, t16, and 117, the gate circuit 9j extracts the output of the third register 9C shown in FIG.

9h and the first and second adders 9g and 9i are always performing calculations, but at times t6 and 117, the gate circuit 9j is activated by the timing pulse to the timing pulse generation circuit 9.
extracts the calculation result ao of the first subtracter 9f and the first adder 9g. Here aQ is time t6. From the output of the second register 9b at time t17 in FIG. 3 (al of C1) and a2 of FIG. 3(b) which is the output of the register 9a, aO=
2a1-a2.

Further, at times t5 and t16, the gate circuit 9j extracts the operation result a10 of the second subtracter -9h and the second adder 91. Here alo is time t5. From the as of FIG. 3 (el, which is the output of the fourth register 9d at time t16) and the as of FIG. 3, ffl, which is the output of the fifth register 9e, atO
It becomes ag-all.

In this way, the gate circuit 9j can obtain the output shown in FIG.
When the level of the signal C2e input to each input terminal of the first subtractor 9f and the second subtractor 9h shown in FIG. 2 is smaller than the level of the signals S and f input to the other input terminals, each subtraction The devices 9f and 9h become borrowed. Further, when the level of the signals C and e inputted to the input terminal is much larger than the level of the signals S and f inputted to the other input terminals, the first and second adders 9g and 9i are in an overflow state. becomes. In such a state, correct calculations are not performed and the correction value of the extrapolation section becomes an abnormal value.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it prohibits the operation output from being applied to the adder when the subtracter is in a borrow state, and also prevents the operation output from being applied to the adder when the adder is in an overflow state. provides an extrapolation calculation circuit for a digital convergence device that prevents abnormal correction values from being output by setting all the outputs of these adders to a high level.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Fifth
The figure is a detailed diagram of a horizontal extrapolation calculation circuit according to an embodiment of the present invention, in which 9a, 9b, 9c, 9d, and 9e are the first to fifth registers, and 9f and 9h are the first to fifth registers. The second subtractor, 9g, 9i are the first
．． The second adder, 9j is a gate circuit, and 9 is a timing pulse generation circuit, which are the same as the conventional circuit. Also, 91.9m is the 1st. A borrow detection circuit detects the pollo state of the second subtracters 9f and 9h, and 9n and 9p are the subtracters 9f when there is an output from the circuit 91.9m.

The input prohibition circuits 9Q and 9r prohibit the output of the adder 9h from being input to the adders 9g and 9i. second adder 9g,
The overflow detection circuits 9s and 9t detect the overflow of the adders 9g and 9i when the -F circuits 9q and 9r have outputs.
This is a high level output circuit that outputs 1 level).

FIG. 6 is a conceptual diagram of the operation of the horizontal extrapolation calculation circuit.

Next, the operation of this device will be explained. First, the drawbacks of the conventional method will be explained in more detail. FIG. 6 is the same conceptual diagram as FIG. 4. Now, the adjustment value on the screen (convergence correction current)
will be explained as shown in FIG. 6 (bl). Assume that the amount on the screen is also smaller than the adjustment value a1a9 of the outer points than the m integer value a2.all of the inner points adjacent to each of them. At this time, As explained in FIG. 2, the output of the first subtractor 9f is al
-aB, but a 1a 2 <0, resulting in a borrow state.

At this time, assuming that the first subtractor 9f is an n-ary subtracter,
The output is 2n+ (al -82) where al, aB<21. Similarly, the output of the second subtractor 9h is also 2n + (aB-88).

Next, the value of adjustment value a1□ aB becomes adjustment value a2. A case where aB is much larger than aB will be described. The output of the first adder 9g, which is an n-ary adder, is 2a1-aB, but since al)>82, 2n<2al-aB, resulting in an overflow state. At this time, the output of the first adder 9g becomes (2a1-aB)-2n. Similarly, the output of the second adder 91 is (2a9-28
)-2n.

Two examples of convergence correction when the subtracters 9f and 9h are in a borrow state are shown in FIG.

At this time, the outputs of adders 9g and 9i are respectively aO=2n+ (2al aB) alO=2n+ (2a9-aB) So, the same figure ~) is aB>al>a2/2 aB>aB>a8/2 An example of when the figure becomes (C1 is a2/2>al a　8　/　2　＞　a　g This is an example of when

FIG. 6(d) shows the state of convergence correction when the adders 9g and 9i are in an overflow state, and the extrapolated values ao and alo at that time are written in the figure. As described above, in the conventional circuit, the extrapolation calculation circuit may not operate normally depending on the adjustment value within the screen.

However, according to the present invention, when the subtracters 9f, 9h are in the borrow state, the input prohibition circuits 9n, 9p operate according to the output of the borrow detection circuit 91.9m, and the outputs from the subtracters 9f, 9h are outputted from the adders 9g, 9h. Not input to 91, adder 9g
, 9i output is al.

It becomes aB. The extrapolated values at this time are az and ay, and are written in FIG. 6 (bl (C1).Adder 9g.

91 is in an overflow state, the outputs of the overflow detection circuits 9Q and 9r cause the high level output circuits 9s and 91 to be in an overflow state.
9t operates and makes the outputs of adders 9g and 9i all high level, in this case adder 9g.

Since 91 is an n-ary adder, its value is (2n-1). The extrapolated values at this time are aX, aW, and Fig. 6 f
Fill in dl.

As described above, in this embodiment, the subtracter is a component of the extrapolation circuit of the digital convergence device.

When the adder enters a borrow or overflow state, the output of the extrapolation calculation circuit is controlled to prevent abnormal convergence correction current from flowing, so convergence correction can be easily adjusted and highly accurate convergence correction can be achieved. becomes possible.

The above embodiment is an example for a horizontal extrapolation calculation circuit, and next, an embodiment for a vertical extrapolation calculation circuit is shown in FIG. In the figure, 9 is a horizontal extrapolation calculation circuit, 10 is a line memory, and 12 is a vertical interpolation calculation circuit, which are the same as in FIG. Also, in the vertical extrapolation calculation circuit 11, subtracters 11a and 11
b. The adder 11C1lid is equivalent to the conventional one.

lie,, 11 [are borrow detection circuits, l1g, llh
is an input prohibition circuit, lli and llj are overflow detection circuits, and llk and 111 are high level output circuits.

Since the circuit operation is the same as that of the horizontal extrapolation calculation circuit 9, the explanation thereof will be omitted.

[Effects of the Invention] As described above, according to the present invention, in the extrapolation circuit of a digital convergence device, when the subtracter and the adder are in a borrow state and an overflow state, respectively, the subtraction layer and the adder are Since the output is controlled to prevent abnormal convergence correction current from flowing, convergence correction can be easily adjusted and highly accurate convergence correction can be achieved.

[Brief explanation of drawings]

Figure 1 is a block diagram of the entire digital convergence device.
Fig. 2 is a block diagram of a conventional horizontal extrapolation calculation circuit, Figs. 3 and 4 are timing diagrams and conceptual diagrams for explaining the operation of the horizontal extrapolation calculation circuit, and Fig. 5 is an embodiment of the present invention. A configuration diagram showing an example, FIG. 6 is a WA for detailed explanation of the present invention.
FIG. 7 is a block diagram showing an embodiment of the present invention applied to a vertical extrapolation calculation circuit. 9f, 9h... 1st. Second subtractor, 9g, 9i...
1st. Second adder, 9n, 9p...input prohibition circuit, 9
Q, 9r... overflow detection circuit, 9S, 9t.
...High level output circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a digital convergence device that digitally performs convergence correction of a color television receiver, an extrapolation calculation circuit that calculates the off-screen correction by extrapolation, and which uses an extrapolation calculation circuit that calculates the off-screen correction by extrapolation. A subtraction circuit that subtracts the correction value from the correction value of the adjustment point adjacent thereto, an addition circuit that adds the calculated value obtained by the subtraction circuit and the correction value of the nearest adjustment point, and the subtraction circuit are in a borrow state. and a high-level output circuit that sets all of the calculation outputs to a high level when the addition circuit is in an overflow state. Extrapolation calculation circuit for digital convergence equipment.