JPH04364685A - Scanning line interpolation device - Google Patents

Abstract

PURPOSE:To improve the deterioration in a vertical high frequency component and a rugged sense in an oblique edge. CONSTITUTION:A delay circuit 101 delays a digital video signal in a rate of a clock signal and delay signal strings X(-n)-X(n) are outputted, and a delay circuit 102 delays a digital video signal for one horizontal period to obtain delay signal strings Y(-n)-Y(n). An oblique difference circuit 103 receives the relevant delay signal strings to obtain an absolute value of each difference signal between picture elements corresponding to the vertical direction and the oblique direction. An oblique direction discrimination circuit 104 discriminates a picture element with strongest correlation from each absolute value. An interpolation picture element is generated-in an oblique sum circuit 110 by using the picture element. The oblique difference circuit 103 generates a difference signal between pseudo picture elements by a phase of 0.5 clock to improve the discrimination accuracy. Moreover, a forced vertical sum circuit 109 is provided between the oblique direction discrimination circuit 104 and the oblique sum circuit 110 to obtain a vertical sum interpolation picture element at a vertical edge part and at an area in which discrimination of correlation is unstable forcibly.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a progressive scan conversion circuit that converts a television signal sent in an interlaced manner to a non-interlaced signal. Regarding equipment.

0002

2. Description of the Related Art In a progressive scan conversion circuit that converts an interlaced television signal into a non-interlaced television signal, a scanning line interpolation process is used to interpolate between signals sent in interlaced scanning. It has become. Therefore, such a progressive scan conversion circuit requires an interpolation signal generation circuit for generating an interpolation line signal.

A motion adaptive progressive scan conversion circuit has separate interpolation signal generation circuits for moving images and still images, and generates interpolation signals from the previous field signal for still images and from the current field signal for moving images. are doing. Here, the interpolation signal generation circuit for the moving image mode will be explained. Conventionally, circuits using a double swing method and circuits using an upper and lower sum method have been considered. However, the interpolation signal generation circuit using the two-degree swing method has a problem in that many aliased components remain, and in particular, signals with diagonal edges are displayed in a jagged manner, creating an unnatural appearance.

On the other hand, in the interpolation signal generation circuit using the vertical sum method, although the unnaturalness of the jaggedness caused by the aliasing component is improved to some extent, the unnaturalness still remains, and the vertical high-frequency components are considerably attenuated. There was a problem when I did that. As explained above, conventional scanning line interpolation circuits for moving images have problems such as jaggedness of diagonal edges and attenuation of vertical high frequency components.

Therefore, the present invention adapts to the image pattern of the input video signal and switches the pixels that perform scanning line interpolation in the diagonal direction, thereby solving the conventional problem of jaggedness of diagonal edges and vertical high-frequency components. It is an object of the present invention to provide a scanning line interpolation device that can improve deterioration.

[0006]

[Means for Solving the Problems] The present invention takes as input a digital video signal sampled with a predetermined clock signal and the number of quantization bits, and generates 2n+1 taps (n is a natural number) that are delayed at the rate of the clock signal. a first delay circuit that outputs a first delayed signal train to each tap;

[0007] The input device receives an m horizontal period delay signal (m is a natural number) of the digital video signal, has 2n+1 taps that are delayed at the rate of the clock signal, and outputs a second delay signal sequence to each tap. 2 delay circuits, and the first delay circuit.
and a differential means for obtaining absolute value difference signals between pixels corresponding to vertical and diagonal directions by inputting the delayed signal train and the second delayed signal train; and each absolute value difference signal obtained from the difference means. a determining means for determining the corresponding pixel with the strongest correlation by comparing the pixels; and using the determination result of this determining means, the first
, an interpolation means for obtaining an interpolation signal by averaging the sum of pixels corresponding to the determination result in the second delayed signal sequence,

The difference means obtains a signal obtained by adding a difference signal between certain taps and a difference signal between other taps, and converts this signal into a sample at a sampling rate of 0.000 to improve the accuracy of correlation determination in the determination means. A means is provided for adding a difference signal between pixels assuming a pixel having a phase of five clocks as a correlation determination element to the determination means.

[0009] The present invention also provides that when the judgment result of the judgment means for judging pixels with strong correlation is given to the interpolation means, when there are many pixel components that are likely to cause misjudgment when performing correlation judgment in the diagonal direction, A means is provided for forcibly switching to a determination result indicating a high correlation between the upper and lower pixels.

[0010] Furthermore, in the present invention, when the judgment result of the judgment means for judging strongly correlated pixels is given to the interpolation means, if there is a vertical high frequency component and interpolation in the diagonal direction is performed, the diagonal edges of the image become jagged. If the result becomes unnatural, means is provided for forcibly switching to a determination result indicating a large correlation between the upper and lower pixels.

[0011]

[Operation] When the correlation of images is detected and interpolation is performed in a diagonal direction using the above means, the accuracy of correlation determination is improved because the correlation determination information includes information for 0.5 clocks. Further, in a region where correlation determination in an oblique direction is unstable, the average output of the sum of pixels between the upper and lower sides is obtained as an interpolation signal, so that the operation is stable. Furthermore, there is no deterioration of vertical high-frequency components, and there is no deterioration in image quality due to judgment errors, and the quality of the interpolated signal is improved.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A digital video signal sampled at a predetermined sampling clock is input to the input terminal 120. The digital video signal is guided to the first delay circuit 101. The first delay circuit 101 delays the video signal in units of sampling clocks and outputs a large number of required first delayed signals 12.
Generates 2.

A 1H delayed video signal is input to the input terminal 121. This video signal is the previous digital video signal delayed by one horizontal period. This signal is input to the second delay circuit 102. The second delay circuit 102 delays the video signal in units of sampling clocks and generates a large number of required second delay signal outputs 123.

First and second delayed signal outputs 122 and 123
is input to the diagonal difference circuit 103. Diagonal differential circuit 1
03 calculates the vertical and diagonal differences centered on the pixel to be interpolated from the first delayed signal output 122 and the second delayed signal output 123, and outputs a large number of diagonal difference signals 124. The diagonal direction determination circuit 104 uses the diagonal difference signal 124 obtained from the diagonal difference circuit 103 to determine a direction with high diagonal correlation, and outputs the diagonal direction determination signal 12.
Outputs 5.

The first delayed signal output 122 is also input to the first horizontal edge detection circuit 106. The first horizontal edge detection circuit 106 detects a horizontal edge component from the first delayed signal output 122 and outputs a first horizontal edge detection signal 126. The second delayed signal output 123 is also input to the second horizontal edge detection circuit 107. The second horizontal edge detection circuit 107 detects a horizontal edge component from the second delayed signal output 23 and outputs a second horizontal edge detection signal 127.

First and second horizontal edge detection signals 126,
127 is input to the diagonal edge detection circuit 108. The diagonal edge detection circuit 108 receives the diagonal direction determination signal 1.
25, it is determined whether there is an edge in the pixels of both lines to be diagonally interpolated, and if the edges do not match on both lines, a second forced upper and lower sum signal 128 is outputted to cancel the diagonal interpolation. do.

Furthermore, the first delayed signal output 122 is also supplied to the false determination prevention detection circuit 105 . The misjudgment prevention detection circuit 105 has a first delay signal output 122 and a second delay signal output 122.
It is determined from the delayed signal output 123 whether the signal is likely to cause errors in detecting the diagonal direction, and a first forced upper/lower sum signal 129 is output according to the result of this determination.

If either the first or second upper/lower sum signal 129 or 128 is output, the forced upper/lower sum circuit 109 forcibly switches the diagonal direction determination signal 125 to the upper/lower sum, and A direction signal 130 is output. Diagonal direction signal 1
30 is input to the diagonal sum circuit 110.

The diagonal sum circuit 110 calculates the average in the diagonal direction using pixels with high diagonal correlation using the diagonal direction signal 130 from the first delayed signal output 122 and the second delayed signal output 123 to obtain a line interpolation signal 131. . This embodiment is configured as described above. Hereinafter, the key blocks of the above system will be explained in detail. FIG. 2 is a more detailed block diagram including the internal configurations of the first delay circuit 101, the second delay circuit 102, the diagonal difference circuit 103, and the diagonal direction determination circuit 104.

In the figure, a first delay circuit 101 is a shift register having a structure in which D-type flip-flop circuits 201 to 209 are connected in series. A digital video signal is input, and first delay signals 2-1 to 2-9 are output from each delay tap. The second delay circuit 102 is a shift register having a configuration in which D-type flip-flop circuits 211 to 219 are connected in series. A 1H delayed digital video signal is input, and second delayed signals 3-1 to 3-9 are output from each delay tap.

The diagonal difference circuit 103 has subtracters 220 to 2.
26 and adders 227 and 228. The outputs of the flip-flop circuits 203 and 219 are sent to a subtracter 226
The outputs of flip-flop circuits 204 and 218 are supplied to a subtracter 225, and the outputs of flip-flop circuits 204 and 218 are supplied to a subtracter 225,
The outputs of 05 and 217 are supplied to a subtracter 224, the outputs of flip-flop circuits 206 and 216 are supplied to a subtracter 223, the outputs of flip-flop circuits 207 and 215 are supplied to a subtracter 222,
The outputs of 8 and 214 are supplied to a subtracter 221, and the outputs of flip-flop circuits 209 and 213 are supplied to a subtracter 220. The outputs of subtracters 222 and 223 are added to adder 2.
27, and the outputs of subtractors 223 and 224 are sent to adder 22.
8.

Outputs 4-1 to 4- of subtracters 220 to 226
7 are supplied to absolute value circuits (ABS) 231 to 237, respectively, and outputs 4-8 and 4-9 of adders 227 and 228
are supplied to absolute value circuits 238 and 239, respectively. The outputs of the subtracter and adder represent the difference signals between the diagonals at each slope. The difference signals 4-1 to 4-9 are output to absolute value circuits 231 to 23 in the diagonal direction determination circuit 104.
Each will lead to 9. The absolute value circuits 231 to 239 are
Take the absolute value of each difference signal.

FIG. 3 shows the direction of diagonal calculation for the pixel currently being interpolated. 2-
The pixels of nodes 3 to 2-9 are represented as X(-3) to X(3), and the pixels of nodes 3 to 3-9 are represented as Y(-3) to Y(3).
Then, the absolute value output signals 41 to 49 of the differences between the slopes are expressed by the following equations. 41= |X(3)-Y(-3)|
=Slope 342= |X(2)-Y(
−2 ) |= slope 243= |X(
1)-Y(-1) |=Slope 144= |X
(0)-Y(-0) | = slope 04
5= |X(-1)-Y(1)|=
Slope −146= |X( −2)−Y(
2) |=Slope-247= |X(-3)-
Y (3) | = slope - 348 = | (X (1) +
X (0)) - (Y (-1) + Y (0)) | = slope 0.
5 49=|(X(-1)+X(0))-(Y(1)+
Y(0)) | = slope -0.5

That is, in the above processing, when detecting a diagonal difference, a diagonal difference output having a phase of 0.5 clocks at the sampling clock rate is also obtained. In this example, the slope of the central pixel in the time axis direction is 0, and the slopes of the central pixel in the time axis direction are 0.5 and -0.5. Comparator 251 in FIG.
is the diagonal difference absolute value signal 48 with a slope of 0.5 and the slope -0.
Compare the value with the diagonal difference absolute value signal 49 of 5 and output the comparison output 6.
Outputs 1.

The comparator 252 compares the values of the diagonal difference absolute value signal 43 with a slope of 1 and the diagonal difference absolute value signal 44 with a slope of 0, and outputs a comparison output 62. Comparator 2
53 compares the values of the diagonal difference absolute value signal 45 with a slope of -1 and the diagonal difference absolute value signal 44 with a slope of 0, and outputs a comparison output 63. The comparator 254 compares the values of the diagonal difference absolute value signal 43 with a slope of 1 and the diagonal difference absolute value signal 48 with a slope of 0.5, and outputs a comparison output 64. The comparator 255 outputs a diagonal difference absolute value signal 45 with a slope of -1 and a slope of -1.
The value is compared with the diagonal difference absolute value signal 49 of 0.5, and a comparison output 65 is output. The comparator 256 outputs a diagonal difference absolute value signal 43 with a slope of 1 and a diagonal difference absolute value signal 4 with a slope of 2.
2 and outputs a comparison output 66. The comparator 257 compares the values of the diagonal difference absolute value signal 45 with a slope of -1 and the diagonal difference absolute value signal 46 with a slope of -2, and outputs a comparison output 67. The comparator 258 outputs a diagonal difference absolute value signal 42 with a slope of 2 and a diagonal difference absolute value signal 41 with a slope of 3.
A comparison output 68 is output. The comparator 259 connects the diagonal difference absolute value signal 46 with a slope of -2 and the slope -
Compare the value with the diagonal difference absolute value signal 47 of 3 and output the comparison output 6.
Outputs 9. Each comparison output is input to direction determination gate 270.

FIG. 4 is a plot of the null point (0 point) of the two-dimensional frequency characteristic of each diagonal difference signal. In the figure, the solid line is a plot of the characteristic that is originally desired to be obtained, and the dotted line shows the aliasing component on the frequency characteristic. As is clear from the figure, there are quite a lot of aliasing components due to differences between lines, so the diagonal direction cannot be easily determined by comparing the differences between diagonals at the same time.

The direction determination gate 270 outputs the comparison outputs 61 to 61.
69 is input, and the diagonal correlation direction is determined. FIG. 5 shows a flowchart representing the processing method of the direction determination gate 270.

The processing of the direction determination gate 270 can be roughly divided into five steps. In step 1, the direction for diagonal determination is determined. In step 2, 0 (corresponding to the sum of the upper and lower sides) is determined for the inclination determination. In step 3, part of 1 and -1 for the slope determination is determined. In step 4, the remaining inclination determinations 1 and -1 are determined. In step 5, slopes 2, 3, -2, and -3 are finally determined.

Now, in FIG. 3, consider four quadrants separated by horizontal and vertical axes with the interpolation pixel as the origin. Slopes of 0.5, 1, 2, and 3 are lines connecting the first and third quadrants (slope to the right), and slopes of -0.5, -1, -2,
-3 is a line (left slope) connecting the second and fourth quadrants. Returning to FIG. 5, a comparison output 61 is obtained in step 1, and this result is the magnitude of the pixel difference between the slope -0.5 and 0.5 (hereinafter, when the slope is written, it also means the pixel difference of the line. This is the result of comparing the two directions, and corresponds to looking at whether the correlation is stronger in the rightward or leftward direction. Assuming that the correlation of the right slope is strong (the slope of 0.5 is small), the comparison result of the slopes of 0 and 1 is determined. Here, if the slope 0 is smaller, the slope determination is determined to be 0. In other words, the correlation between the upper and lower pixels is strong. Conversely, if slope 1 is smaller, the correlation of slope 1 is stronger than that of slope 0, but there is a possibility that slope 2 and slope 3 are even stronger. Therefore, first, the slope is 0.
A comparison result 64 between the slope 5 and the slope 1 is determined. This comparison is
There is a meaning in comparing slope 1 and slope 0 and confirming slope 1. If slope 1 is still small, the comparison output 66 of slopes 1 and 2 is further used to determine whether the correlation between slope 2 is strong or not. When slope 1 is small, slope 1 is derived as the determination result, and when slope 2 is small, it is determined which of slopes 2 and 3 has a stronger correlation. In this way, the inclination is determined one after another, and a sample inclination determination is obtained from the direction determination gate 270. In the above description, the inclination determination for the right tilt side has been described, but the determination for the left tilt side is made in the same way.

FIG. 6 shows the frequency range detected in step 1. By comparing the slope of 0.5 and the slope of -0.5, it is divided into regions as shown in the figure (vertical black line). In step 2, according to the area detected in step 1,
A comparison is made between the slopes of 0 and 1 or -1, and an area with a slope of 0 is determined as shown in FIG.

In step 3, a part of the slope determination 1 is determined by comparing slope 0.5 and slope 1 and slope -0.5 and slope -1. FIG. 8 shows the area after the determination in step 3. In step 4, slope 1, slope 2 and slope -1
The remaining part of the slope determination 1 is determined by comparing the slope and the slope -2. FIG. 9 shows the results of the determination in step 4. The aliasing component at slope 3 in Figure 9 is 1 of the slope judgment.
Therefore, in order to prevent erroneous determination due to this, a part of the area for tilt determination 1 is determined in advance in step 3.

In step 5, slope 2 and slope 3 and slope -2 and slope -3 are compared to determine slope judgment 2 and slope judgment 3. FIG. 10 shows the final determination results. The diagonal direction is determined by the algorithm described above. By doing this, accurate diagonal direction determination is performed in all bands within the field, and Figure 2
The diagonal direction determination signal 12 is output from the direction determination gate 270.
5 is output.

In particular, in this determination, the diagonal difference output for detecting the diagonal correlation is assumed to be a pixel whose phase is 0.5 clocks of the sampling rate, and a difference signal between the pixels is created. Since this information is added as an element for tilt determination, area determination (tilt determination) becomes accurate. This system has further distinctive features.

FIG. 11 shows the output X(
-2), X(2), and output Y from delay circuit 123
Misjudgment prevention circuit 105 to which (-2) and Y(2) are input
FIG. 2 is a block diagram showing the internal configuration of the computer. X(2) and Y(-2) are input to the subtracter 301. Subtractor 302
, X(-2) and Y(2) are input. Adder 31
2, X(2) and Y(-2) are input. Adder 3
14, X(-2) and Y(2) are input. The output of the subtracter 301 is input to an absolute value circuit 305, the output of the subtracter 302 is input to an absolute value circuit 306, each absolute value output is input to a subtracter 320, and this output is input to an absolute value circuit 310.
The absolute value is taken at . The outputs of adders 312 and 314 are input to a subtracter 316 for subtraction processing, and the result is input to an absolute value circuit 318. And absolute value circuit 31
The outputs of 0 and 318 are input to a comparator 319 and compared. Subtractors 301, 302, absolute value circuits 305, 30
6. The subtracter 320 and the absolute value circuit 310 perform calculations as shown in the following equation. ||X(2)-Y(-2)|-|X(-2)-Y(
2)｜｜

FIG. 12 shows the frequency components extracted by this calculation. The part surrounded by the dotted line shows the aliasing component of this frequency characteristic. This calculation is designed to extract the level of a component around 525/4 as a vertical frequency component. On the other hand, the adder 312, the adder 314, the subtracter 320, and the absolute value circuit 318 perform calculations as shown in the following equation. |(X(2)-Y(-2))|-|(X(-2)-
Y(2)) |

FIG. 13 shows the frequency components extracted by this calculation. The part surrounded by the dotted line shows the aliasing component of this frequency characteristic. In this calculation, a component centered around a vertical frequency of 525/8 is extracted from the low range of the diagonal component as a frequency component.

Comparator 319 in FIG. 11 compares this absolute value circuit output 321 and absolute value circuit output 311,
As a result, if the component around 525/4 is large,
A forced upper/lower sum signal 129 is output that stops the diagonal interpolation and forcibly performs the interpolation of the upper/lower sum. In response, the forced upper/lower sum circuit 109 provides a control signal to the diagonal sum circuit 110 to indicate that the sum of the pixels between the upper and lower pixels is to be used as an interpolation signal.

In the diagonal direction detection, as can be seen from FIG. 10, the judgment direction is discontinuous due to turning back with 525/4 being Sakai. For this reason, for signals that have many frequency components in the area around 525/4, it is unstable as to which side the diagonal direction will be determined, and the interpolation signal that is output depends on which direction the diagonal direction is taken. There is a big difference.

Therefore, when comparing the low frequency component of the signal component in the diagonal direction with the signal component around 525/4, if the component around 525/4 is large, the diagonal interpolation is stopped and the sum of the upper and lower parts is By forcibly performing interpolation, instability of the interpolation operation can be eliminated.

In picture-adaptive scanning line interpolation, diagonal interpolation is particularly effective for signals having edges in the diagonal direction. In terms of frequency characteristics, the edge signal in the diagonal direction has frequency components in the diagonal direction from the low range to the high range, and generally has a lot of energy on the low range side. For this reason, the diagonal edge components to be interpolated are distinguished from the components near 525/4 that are likely to cause a judgment error, and only the necessary components are interpolated between the diagonals. As a result, diagonal interpolation is stopped in areas where direction determination is unstable, and it is possible to prevent disturbances from occurring on the screen due to fluctuations in the determination direction in these areas. This system also has additional distinctive features.

FIG. 14 shows the first horizontal edge detection circuit 1
06, a block diagram showing the internal configuration of the second horizontal edge detection circuit 107 and the diagonal edge detection circuit 108. In the figure, the subtracter 401 contains 2-1 and 2.
-4 signal is input and the difference is taken. As a result, a horizontal high-frequency component is extracted, further inputted to an absolute value circuit 403 to take an absolute value, and compared with a predetermined value in a comparator 405 to obtain a first horizontal edge detection signal 126. On the other hand, the subtracter 406 receives the signals 3-1 and 3-4 and calculates the difference. This extracts the horizontal high frequency components,
Furthermore, it is input to the absolute value circuit 407 and the absolute value is taken.
A comparator 409 compares it with a predetermined value, and a second horizontal edge detection signal 127 is obtained.

The diagonal edge detection 108 uses shift registers 411 to 416 and data selector 42 connected in series.
4, and shift registers 426 to 431 connected in series.
and a selector 439. The output of the comparator 405 is input to a group of shift registers 411 to 416, and the output of each stage is input to a selector 424. The output of the comparator 409 is input to a group of shift registers 426 to 431,
The output of each stage is input to a selector 439. The selectors 424 and 439 are controlled by the diagonal direction determination signal 125 supplied from the diagonal direction determination circuit 104, and detect whether the signal of the pixel for which the diagonal sum is to be calculated has an edge component. In other words, the selector 42
Signals 440 and 441 output in combination from 4 and 439
is input to the AND circuit 442 and logically multiplied. The second forced vertical sum signal 128 can be output only when the signals to be diagonally summed between the pixel columns of the upper and lower lines do not have horizontal edge components. The fact that the signals to be diagonally summed between the pixel columns of the upper line and the lower line both have horizontal edge components means that a diagonal edge exists. Also, one side of the AND circuit 442 is 1
, the other being 0 means that neither has a horizontal edge component, but has an edge in the vertical direction.

FIGS. 15A, 15B, and 15C are diagrams showing what kind of interpolation is performed when an actual signal is input. In FIG. 15A, a signal with diagonal edges is normally subjected to diagonal interpolation processing using an interpolation line. Figure (B) is an example in which only one black line is placed (there is an edge in the vertical direction). In this case, the diagonal direction determination signal 125 is interpolated with white because the 0H line is always white beyond the black line, and the pixel correlation is close to white. In such a case, although the pixel levels are close, interpolation is performed between the edge portion of the 1H signal and the non-edge portion of the 0H signal, resulting in a visually unnatural image. As described above, if the pixels to be diagonally summed by the second forced upper-lower sum signal 128 do not have edges, the upper-lower sum is forcibly performed. For this reason, the image looks like the one shown in FIG. Figure 1
In the signals shown in 5(A), both edges are removed, so normal diagonal interpolation can be performed without any problem.

As described above, the present invention provides (1) a diagonal difference output for diagonal correlation detection at a sampling rate of 0.
Pixels having a phase of 5 clocks are assumed in a pseudo manner, and a difference signal between the pixels is created. Since this information is added as an element for tilt determination, area determination (tilt determination) becomes accurate. Moreover, it can be realized with a small circuit scale. (2) Low-frequency components of diagonal signal components and 525/4
If the component around 525/4 is large compared to the surrounding signal components, interpolation between diagonals is stopped and interpolation between the upper and lower sums is forced, thereby eliminating instability in the interpolation operation. . (3) When the pixels for which diagonal summation is to be performed do not have edges, the summation between the upper and lower parts is forcibly performed to eliminate the unnatural feeling caused by interpolation.

As described above, the present invention enables accurate diagonal correlation detection with a small circuit scale, eliminates unnatural diagonal interpolation and flickering due to error determination, and effectively performs diagonal interpolation. By doing this, it is possible to eliminate the jagged appearance of diagonal lines caused by progressive scan conversion and obtain smooth progressive scan conversion of images.

[0047] This invention also applies to the above (1), (2), and (3).
) It is not necessary to have all of the characteristic functions mentioned above at the same time, and if any one of them is applied to the system, sufficient effects can be obtained. Furthermore, various modified embodiments are possible for the functions of the circuits shown in each FIG.
The number of pixels to be used is not limited to this, and the slope is not limited to 0.5, but various settings such as 1.5, 2.5, etc. are also possible. Furthermore, the configuration example of the misjudgment prevention detection circuit 105 shown in FIG. 11 and the number of pixels used are not limited to these. The same applies to the circuit configuration shown in FIG.

[0048]

Effects of the Invention As explained above, the present invention adapts to the image pattern of the input video signal and switches the pixels that perform scanning line interpolation in the diagonal direction, thereby solving the problem of the jagged appearance of diagonal edges, which has been a problem in the past. , it is possible to improve the deterioration of vertical high frequency components.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of the circuit of FIG. 1 in detail.

FIG. 3 is an explanatory diagram shown to explain the operation when the circuit in FIG. 1 obtains an inter-pixel difference.

FIG. 4 is a diagram showing the characteristics of the diagonal differential circuit in FIG. 1;

FIG. 5 is a determination operation explanatory diagram shown to explain the operation of the diagonal direction determination circuit in FIG. 1;

FIG. 6 is an explanatory diagram showing a determination area in a first step of the diagonal direction determination circuit in FIG. 1;

FIG. 7 is an explanatory diagram showing a determination area in a second step of the diagonal direction determination circuit in FIG. 1;

FIG. 8 is an explanatory diagram showing a determination area in a third step of the diagonal direction determination circuit of FIG. 1;

FIG. 9 is an explanatory diagram showing a determination area in a fourth step of the diagonal direction determination circuit in FIG. 1;

FIG. 10 is an explanatory diagram showing a determination area in a fifth step of the diagonal direction determination circuit of FIG. 1;

FIG. 11 is a circuit diagram showing a specific example of the detection circuit for preventing erroneous determination shown in FIG. 1;

FIG. 12 is a frequency characteristic diagram shown to explain the operation of the false determination prevention detection circuit of FIG. 1;

13 is a frequency characteristic diagram shown for explaining the operation of the false determination prevention detection circuit shown in FIG. 1; FIG.

14 is a circuit diagram showing a specific example of the horizontal edge detection circuit and diagonal edge detection circuit of FIG. 1. FIG.

FIG. 15 is an explanatory diagram schematically showing an example of a pixel arrangement for explaining the operation of the circuit shown in FIG. 14;

[Explanation of symbols]

101, 102...delay circuit, 103...diagonal differential circuit, 1
04...Diagonal direction determination circuit, 105... Misjudgment prevention detection circuit, 106, 107... Horizontal edge detection circuit, 108... Diagonal edge detection circuit, 109... Forced upper and lower sum circuit, 110
...diagonal sum circuit.

Claims (4)

[Claims] 1. A digital video signal sampled with a predetermined clock signal and a number of quantization bits is input, and has 2n+1 taps (n is a natural number) that are delayed at the rate of the clock signal, and each tap has a first a first delay circuit that outputs a delayed signal sequence of , and 2n+1 taps that receive an m horizontal period delay signal (m is a natural number) of the digital video signal and delay at the rate of the clock signal;
a second delay circuit that outputs a second delay signal train to each tap; a second delay circuit that receives the first delay signal train and the second delay signal train; a difference means for obtaining an absolute value difference signal; a determination means for comparing each absolute value difference signal obtained from the difference means to determine the corresponding pixel with the strongest correlation; 1. In a scanning line interpolation device comprising an interpolation means for obtaining an interpolation signal by averaging the sum of pixels corresponding to the determination result in the second delayed signal sequence, the difference means calculates the correlation in the determination means. In order to improve the judgment accuracy, a signal was obtained by adding the difference signal between one tap and the difference signal between other taps, and this signal was pseudo-assumed to be a pixel with a phase of 0.5 clocks of the sampling rate. A scanning line interpolation device characterized by comprising means for adding a differential signal between pixels to the determining means as a correlation determining element. 2. A first delayed signal train having 2n+1 taps (n is a natural number) which inputs a digital video signal sampled with a predetermined clock signal and the number of quantization bits and delays at the rate of the clock signal. X(-n)～X(
n), and a second delay signal sequence Y(-n ) to Y(n), and inputs the first delayed signal string and the second delayed signal string, performs the calculation shown by the formula, and calculates 2n+1 differences between each of them. a first absolute difference calculation means that outputs an absolute value; the first delayed signal string and the second delayed signal string are input; |
a second absolute difference calculation means for performing an operation represented by the formula: X(1)+X((0)-Y(-1)-Y(0)|; a third absolute difference calculation means for inputting the delayed signal sequence |X(-1)+X((0)-Y(1)-Y(0)|); The output of the absolute difference calculation means, the output of the second absolute value calculation means, and the output of the third absolute difference calculation means are input, and image correlation determination output G from -n to n
Accordingly, the apparatus further comprises interpolation signal generating means for generating a scanning line interpolation signal by performing the calculation of (X(G)+Y(-G)/2) on the first delayed signal string and the second delayed signal string. A scanning line interpolation device characterized by: 3. A first delayed signal train having 2n+1 taps (n is a natural number) that receives a digital video signal sampled with a predetermined clock signal and a number of quantization bits as input, and is delayed at the rate of the clock signal. X(-n)～X(
a second delay signal sequence Y(-n) having 2n+1 taps which input the one horizontal period delay signal of the digital video signal and delay it at the rate of the clock signal; A second delay circuit that outputs ~Y(n), receives the first delayed signal train and the second delayed signal train, determines the correlation direction of the image, and generates an image correlation determination signal from -n to n. an image correlation determination circuit that outputs G;
input the delayed signal train and the second delayed signal train,
||X(m)-Y(-m)|-|X(-m)-Y(m)
a first arithmetic means that performs an operation represented by the formula ||; inputs the first delayed signal string and the second delayed signal string;
||X(m)+Y(-m)|-|X(-m)+Y(
m) a second calculation means that performs the calculation represented by the formula ||;
The output of the first calculation means and the output of the second calculation means are compared, and if the output of the first calculation means is smaller, a slope of 0 is output as the addition direction signal G of the corresponding pixel; In other cases, a means for outputting an addition direction signal G as an image correlation determination signal, and a means for outputting an addition direction signal G as an image correlation determination signal, and (X( 1. A scanning line interpolation device comprising: interpolation signal generating means for generating a scanning line interpolation signal by performing the calculation of G)+Y(-G))/2. 4. A first delayed signal sequence that receives as input a digital video signal sampled with a predetermined clock signal and the number of quantization bits, and has 2n+1 taps (n is a natural number) that is delayed at the rate of the clock signal. X(-n)～X(
a second delay signal sequence Y(-n) having 2n+1 taps which input the one horizontal period delay signal of the digital video signal and delay it at the rate of the clock signal; A second delay circuit outputting ~Y(n), and inputting the first delayed signal sequence and the second delayed signal sequence, determine the correlation direction of the image, and perform image correlation determination from -n to n. an image correlation determination circuit that outputs an addition direction signal G; a first edge detection circuit that detects a horizontal edge component from the digital video signal; and a first edge detection circuit that detects a horizontal edge component from the one horizontal period delayed signal. A second edge detection circuit, the output of the first edge detection circuit, the output of the second edge detection circuit, and the addition direction signal G are input, and the corresponding pixels of X(G) and Y(-G ), and if an output from the diagonal edge determination circuit cannot be obtained, outputs a slope of 0 to the addition direction signal G. ( 1. A scanning line interpolation device comprising: interpolation signal generating means for performing the calculation of X(G)+Y(-G))/2 and generating a scanning line interpolation signal.