JPS61103380A - Video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent transient deviation of a reproduced picture produced at joints of edition by recording the 1st and 2nd vertical synchronizing signals to be distinguished near a head scanning end location of each video track and near the head scanning start position. CONSTITUTION:A reproduced composite synchronizing signal is fed to an automatic frequency control circuit 12, from which a continuous wave of 2fH is generated and fed to vertical synchronous separator circuits 12, 13, and when 3-5 vertical pulses are counted, pulses P1, P3 are generated respectively. The pulses P1, P3 are synchronized with the continuous wave 2fH to generate signals SYDV1, SYDV2, which are fed to a phase comparator circuit 16 and an AND circuit 17. A window pulse from a timing circuit 15 is fed to another input of the AND circuit 17, an output PRST 2 of the AND circuit 17 resets a counter 14, and the self-running of the counter 14 decides the phase of an output signal VOUT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal recording and reproducing device, and is particularly suitable for application to a video tape recorder (VTR).

[Conventional technology]

For example, a 1-head Ω type helical VT is used as a VTR for broadcasting stations.
There is R. In this one-head Ω-type helical TR, since the tape is not wrapped around the entire circumference of the drum, the open signal is actually missing for a period of about 0.5 to 0.8 (ms). This omission occurs in the vertical blanking interval, and the vertical synchronizing signal is recorded near the head scanning end position of each recording track.

In this type of VTR, one field of video signals is usually recorded on one video track, and the playback video signal from the next track is synchronized based on the vertical synchronization signal recorded on the previous track. I am getting .

[Problem that the invention seeks to solve]

However, conventional VTRs that obtain synchronization based on a vertical synchronization signal recorded near the end position of the head scan on a tape track have the following problems.

(1) Unable to respond to sudden jerks that occur at seams during editing.

In order to track the playback head, a control (CTL) signal is recorded along the length of the tape by the pulse output of a pulse generator that represents the rotational phase of the drum. It is designed to be used in succession. However, in reality, video signals recorded on multiple VTRs can be transferred to a common editing VTR.
When editing spliced shots, each VT used during recording
Since there are differences in operating characteristics between the R CTL signal recording system and the editing VTR tracking system, there is a risk that the track spacing on the edited tape may deviate from the standard value.

As shown in FIG. 4, for example, when recording the track of cut C2 following the recording track in which the video signal of cut C1 is recorded, the head establishes tracking while reproducing the track of cut C1, and then Record. However, at this time, the pulse generator used to record the CTL signal of cut C1 and the
Due to the difference in characteristics between C2 and the pulse generator used for CTL signal recording, the first track T (
N+1) and the last track TN of cut C1 may not match the standard spacing T.

For example, as shown in FIG.
) is T+ΔT, which is ΔT larger than the standard interval T, the recording start position of track T(N+1) is track TN.
ΔT cosecθ (here, θ is the track angle, for example, 2 degrees and 34 minutes). Therefore, when this tape is reproduced, a phase shift of ΔT cosecθ occurs at the seam from cut C1 to cut C2.

In general, in a VTR, if the phase shift is steady, it can be corrected using, for example, a time base correction device, but if a large phase shift suddenly occurs like this, it cannot be corrected.

In particular, with HD (high-definition) VTRs, the IH length on the video track is short, so if the same mechanism is used, NT
Compared to an SC type VTR, the effect of phase shift at the seam is greater, and in reality, it is on the order of IH. Therefore, if the vertical synchronization signal is recorded near the head scanning end position, there is a risk that the reproduced image will be transiently shifted in the vertical direction due to this phase shift.

(2) Vertical synchronization signals cannot be reproduced during reproduction in variable speed reproduction mode using a dynamic tracking (DT) head.

In a VTR having a variable speed playback mode, the running speed and running direction of the tape can be changed as necessary during playback. In this case, a DT head is used to cause the playback head to track a recording track recorded at a normal speed while running the tape at a speed other than the normal speed (including still speed).

However, with this method, when the tape running speed becomes slower than the normal speed or the tape running direction becomes reverse, the length of the scanning locus on the recording track tracked by the DT head becomes shorter than the length of the recording track. Therefore, it becomes impossible to reproduce the vertical synchronization signal recorded at the end of the scan.

For example, in the still mode, as shown in FIG. 5, the scanning trajectory TR3 of the reproducing head is formed so as to cross one recording track, so that the recording head is recorded at the end of the scanning of the track TX being tracked. The vertical synchronization signal that is being played will no longer be playable.

Note that this problem also occurs in other variable speed playback modes.

The present invention has been made in consideration of the above-mentioned problems (1) and (2), and is intended to provide a video signal recording and reproducing apparatus that can solve these problems all at once.

[Means for solving problems]

In order to achieve this object, the present invention records distinguishable first and second vertical synchronization signals VSYNC1 and VSYNC2 near the head scan end position and the head scan start position of each video track of the magnetic tape, respectively. Regenerated first and second vertical synchronization signals VSYNCI
, VSYNC2 to perform video signal processing.

[Effect]

First vertical synchronization signal VSYNCI and second vertical synchronization signal V
Both SYNC2 act as vertical synchronizing signals. Since the second vertical synchronization signal VSYNC2 is provided near the head scanning start position of the video track, when video signal processing is performed using this signal, it is possible to prevent transient shifts in the reproduced image that occur at editing seams.

Furthermore, since two vertical synchronization signals are provided, the opportunity to reproduce the vertical synchronization signal can be greatly increased even when the DT head is in the variable speed reproduction mode.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. 1st
The figure shows the format of, for example, an HD recording signal used in the apparatus of the present invention, and particularly shows the signal format before and after the vertical blanking period.

This recording signal is the first and second vertical synchronization signal
5YNCI and u VSYNCC2@Murasuke 1') The 1st period signal VSYNCI consists of 5 vertical synchronizing pulses P, similar to the conventional recording signal format, and vertical synchronization pulses from even fields to odd fields. In the blanking period VBLKI (Fig. 1 (A)), for example, from 1123H to 1125H (Fig. 1 (B)
)), and the vertical blanking period VBLK is inserted from the odd field to the even field.
2 (Figure 1 (C)), for example, from 560H to 5
62H (FIG. 1(D)).

The second vertical synchronization signal VSYNC2 consists of, for example, three vertical synchronization pulses vP, and the first vertical blanking period V
In BLKI, for example, 34H and 35H (FIG. 1 (B)) are inserted, and in the second vertical blanking period VBLK2, for example, 595H and 596H (
It is inserted in the period shown in FIG. 1(D)).

Here, the number of vertical synchronization pulses in the second vertical synchronization signal VSYNC2 is selected to be three in order to distinguish it from the first vertical synchronization signal VSYNCI. Second, the first vertical synchronization signal VSY like 4 and 6
This is because if the number of vertical synchronization pulses is close to the number of NCI vertical synchronization pulses (5), the number may be incorrectly counted due to noise or the like, and the video signal processing device may make an incorrect judgment. Third, when the number of vertical synchronization pulses is odd, the first vertical blanking period VBLKI and the second vertical blanking period VB
This is because the number of horizontal scanning periods used for the vertical synchronization signal is the same for both LK2 and the number of horizontal scanning periods used for other processing is the same (in FIGS. 1(B) and (D),
(The shaded period indicates the period of use).

The first vertical synchronization signal VSYNCI is an equalization pulse E of 3H before and after 3H to ensure compatibility with conventional recording signals.
It has an equalization period of P. On the other hand, an equalization period is not provided before and after the second vertical synchronization signal VSYNC2 so that even a little effective information can be included.
A video signal comes immediately following the synchronization signal VSYNC2.

The switching position of the video track from an odd field to an even field and the switching position of a video track from an even field to an odd field are determined by the first vertical synchronization signal VS.
It is selected to be at an intermediate position between YNCI and the second vertical synchronization signal VSYNC2. That is, the first vertical synchronization signal VSYN
CI is recorded near the head scan end position of the track,
The second vertical synchronization signal VSYNC2 is recorded near the head scanning start position.

A recording signal having such a format is recorded on a tape in the same way as recording a general video signal, and the second
The only difference is that the vertical synchronizing signal VSYNC2 is recorded during a predetermined horizontal scanning period.

Vertical synchronization signal VSY from the playback signal played from the tape
Separate NCI and VSYNC2 and connect vertical synchronization signal VOUT
As the vertical synchronizing signal output circuit 10 that outputs the , the configuration shown in FIG. 2 can be applied.

In FIG. 2, a vertical synchronization signal output circuit 10 receives a composite synchronization signal C3YNC (FIG. 3(A)) as an input signal, and receives an automatic frequency control circuit 11 and a first vertical synchronization separation circuit 12.
, is applied to the second vertical synchronization separation circuit 13.

The automatic frequency control circuit 11 separates the horizontal synchronization signal H3YNC from the composite synchronization signal csyNC, forms a continuous wave signal 2fI4 having a frequency twice the horizontal scanning frequency (r,) based on the separated signal, and outputs the continuous wave signal 2fI4 to the counter 14, 1 vertical synchronization separation circuit 12 and a second vertical synchronization separation circuit 13.

The counter 14 counts the continuous wave signal 2fH, and when the count value is 1125 (decimal number), provides the pulse signal P2 to the phase comparison circuit 16, and also provides the count contents to the sequential timing pulse generation circuit 15. When the count value reaches a predetermined value, the timing pulse generation circuit 15 supplies the output vertical synchronization output VOUT to the video output processing circuit (for example, a time axis correction device) as an operation reference signal. counter 1
4 is preset by the output signal PR8T1 of the phase comparison circuit 16 and the output signal PR3T2 of the AND circuit 17.

jq The first vertical synchronization separation circuit 12 counts the vertical synchronization pulses VP (FIG. 3(A)), and when there are five vertical synchronization pulses, forms the pulse signal P1 shown in FIG. 3(B), This pulse signal P1 is converted into a continuous wave signal 2.
First vertical synchronization separation signal 5YDVI synchronized with f, 1
(FIG. 3(C)) is applied to the phase comparator circuit 16.

The phase comparator circuit 16 compares the phases of the first vertical synchronization separation signal 5YDVI and the pulse signal P2, and when the phase mismatch continues two or more times, the phase comparison circuit 16 forcibly converts the first vertical synchronization separation signal 5YDV1 to the first vertical synchronization signal VSYNC1. The corresponding preset value PRST is preset to 1 (eg, 1 (decimal)). On the other hand, when the first vertical synchronization separation signal 5YDV1 is not given within a predetermined period, when the phases of the first vertical synchronization separation signal 5YDV1 and the pulse signal P2 match, and when the phase mismatch occurs only once, It is preset to the preset value PR5TI at the timing of the pulse signal P2.

Here, the pulse signal P2 is the past vertical synchronizing signal VSYNCI, VSYNCI, usually one field before.
It is formed based on NC2. On the other hand, the first vertical synchronization separation signal 5YDV1 is formed based on the current vertical synchronization signal VSYNCI. Therefore, it may be affected by skew distortion.

However, in the first vertical synchronization separation circuit 12, the separated first vertical synchronization signal is converted into a continuous wave signal 2fH (0,5
Since the synchronization is performed in H units), even if there is a skew distortion of up to 0.5 H, the phase comparator circuit 16 can obtain a matching output. Therefore, when a steady skew distortion occurs, the counter 14 is preset to its own output P2, that is, it runs free.

Furthermore, even if the first vertical synchronization separation signal 5YDV1 cannot be obtained due to dropout or miscounting of vertical synchronization pulses due to noise, the counter 14 runs on its own and receives the vertical synchronization signal VOUT from the timing pulse generation circuit 15 at a predetermined timing. Output.

On the other hand, if the skew distortion becomes 0.5H or more, for example, the phase comparison circuit 16 determines that the phases do not match. In order to increase the reliability of the judgment, the phase comparator circuit 16 does not stop the free running of the counter 14 when there is a single phase mismatch, and when it judges that there is a phase mismatch two or more times in a row, it uses the output 5YDVI of the first vertical synchronization separation circuit 12. Preset and counter 14
Forcibly set the count value to the preset value.

The second vertical synchronization separation circuit 13 forms a pulse signal P3 (Fig. 3 (D)) when there are three vertical synchronization pulses P, and then synchronizes it with the continuous wave signal 2fw to generate a second vertical synchronization separation signal. 5YDV2 (FIG. 3(E)) is applied to one input terminal of the two-person couple circuit 17. A window pulse wp is applied from the timing pulse generation circuit 15 to the other input terminal of the AND circuit 17.

The timing pulse generation circuit 15 generates the first signal based on the signals coming from the first vertical synchronization separation circuit 12 and the counter
When the vertical synchronization separation signal 5YDV1 is output, the counter 14 calculates the second vertical synchronization signal V by calculating from the time when the counter 14 is preset to the preset value PR3TI.
During a predetermined period before and after the time when the value corresponding to SYNC2 (for example, 71) will be output (in reality, the deviation due to skew distortion is about ±IH, so select ±IH)
, outputs a window pulse wP rising to logic rHJ.

When the first vertical synchronization separation signal 5YDV1 is not obtained, the timing pulse generation circuit 15 outputs a window pulse wP that is opened sufficiently to allow the second vertical synchronization separation signal 5YDV2 to pass.

Therefore, the AND circuit 17 outputs the first vertical synchronization separation signal 5YD.
If V1 cannot be obtained, the second vertical synchronization separation signal 5YDV
2 to set the counter 14 to the second preset value P.
Preset to R3T2 (for example, 71). When the skew distortion is within IH, the window pulse wP based on the first vertical synchronization separation signal 5YDVI is set to logic rH.
Since the second vertical synchronization separation signal 5YDV2 is applied at the time of J, the counter 14 is preset to the second preset value PR3T2.

・、24"-Dfl<Small 8"'Side is 120
Even if the counter 14 is preset to the preset value PR3T2, the continuity of the count value is maintained. If the skew distortion is large, the count value is forcibly changed by this preset. In other words, the latest vertical synchronization signal VSY
The count value is synchronized with NC2.

On the other hand, when the second vertical synchronization separation signal 5YDV2 is not output due to a dropout occurring or when the head is unable to scan during variable speed playback mode, the AND circuit 17 is closed, and in this case, the counter 14 is not a preset value.

In the circuit shown in FIG. 2, the first vertical synchronization separation signal 5Y
If both DV1 and the second vertical synchronization separation signal 5YDv2 are being sent, the counter 14 is preset upon receiving the second vertical synchronization separation signal 5YDV2.

The first vertical synchronization signal VSYN recorded on the same track after being preset with the second vertical synchronization separation signal 5YDV2
Since the first vertical synchronization separation signal 5YDV1 based on the CI is compared with the pulse signal P2, a j-phase coincidence is obtained and is preset by the output of the counter 14. Thereafter, upon receiving the second vertical synchronization separation signal 5YDV2, it is preset again.

Therefore, in this case, the timing of the output signal VOUT is mainly determined by the phase of the second vertical synchronization signal VSYNC2. Here, since the second vertical synchronization signal VSYNC2 is recorded near the head scanning start position of the track, it is sufficient as phase information of the reproduced image. Note that even if a mismatch is obtained in the phase comparator circuit 16, the counter 14 is preset by the second vertical synchronization separation signal 5YDV2, so the output signal VOUT is still the same as the second vertical synchronization signal V.
The timing is determined by the phase of SYNC2.

Even if the first vertical synchronization separation signal 5YDVI is not sent out from this state, the counter 14 is preset upon receiving the second vertical synchronization disturbance signal 5YDV2, and the counter 14 runs freely, and the output signal VOUT is The timing is determined by the phase of the 2 vertical synchronization signal VSYNC2.

On the other hand, when the second vertical synchronization separation signal 5YDV2 is not sent out, the first vertical synchronization separation signal 5YDV
1 and the pulse signal P2 of the counter 14, the phase of the output signal VOUT is determined by the count value generated by free running. When the first vertical synchronization separation signal 5YDV1 becomes out of phase with the pulse signal P1 twice in a row, the counter 14 runs free after being forcibly preset to the preset value PR3TI.

First and second vertical synchronization separation signals 5YDVI 5YDV2
When both are not obtained, the phase of the output signal VOUT is determined by the count value generated by the free running of the counter 14.

Therefore, according to an embodiment in which a signal having the signal format shown in FIG. 1 is recorded on a tape and the vertical synchronization signal output circuit 10 shown in FIG. If so, the phase of the separated vertical synchronization signal is output without changing it, and if the skew distortion is within the range that cannot be corrected, the phase of the vertical synchronization signal is forcibly changed, so that subsequent video signal processing The operation of the circuit can be enabled.

Further, according to this embodiment, since the video signals are synchronized mainly by the second vertical synchronization signal VSYNC2 recorded on the same track, accurate synchronization can be obtained, and the playback video at the editing joint can be synchronized. Misalignment can be effectively prevented.

Furthermore, according to this embodiment, the first vertical synchronization signal VSY
Since the phase of the output signal VOUT can be determined by either the NCI or the second vertical synchronization signal VSYNC2, synchronization in the variable speed playback mode using the DT head can be achieved with higher precision.

Here, according to the circuit shown in FIG. 2, even when a conventional format playback signal including one vertical synchronization signal is given,
It is possible to operate in the same manner as in the case where the second vertical synchronization separation signal 5YDV2 is not provided, and to send out the output signal ■○UT, thereby providing compatibility.

Note that in the above embodiment, the second vertical synchronizing signal VSY
The number of vertical synchronization pulses vp of NC2 is 33 to 1
Although seven pieces are shown, the number is not limited to this, for example, seven pieces may be used.

Further, in the above embodiment, the first and second vertical synchronization separation circuits 12 and 13 are provided separately, but a commonly used vertical synchronization separation circuit is provided, and the vertical synchronization pulse vp
The output may be switched depending on the number of the outputs.

〔Effect of the invention〕

As described above, according to the present invention, the vertical synchronization signal is recorded in a distinguishable manner near the head scan start position and the head scan end position of the video track, so that a stable vertical synchronization signal can be used for various video signal processing. It can be used for In this way, it is possible to effectively prevent misalignment of reproduced images at the joints of the i-panel collection. Further, the vertical synchronization signal can be easily and stably detected even when the DT head is in the variable speed playback mode.

[Brief explanation of the drawing]

FIG. 1 is a route diagram showing the format of a recording signal used in an embodiment of a video signal recording/reproducing device according to the present invention, FIG. 2 is a block diagram showing a vertical synchronization signal output circuit in this embodiment, and FIG. 3 2 is a signal waveform diagram of each part of the circuit of FIG. 2, and FIGS. 4 and 5 are route diagrams for explaining the drawbacks of the conventional device. VSYNCI, VSYNC2---Vertical synchronization signal, 11---Automatic frequency control circuit, 12.
13... Vertical synchronization separation circuit, 14...
Counter, 15...timing pulse generation circuit, 16...phase comparison circuit, 17...AND circuit.

Claims (1)

[Claims] Distinguishable first and second vertical synchronization signals are recorded near the head scan start position and near the head scan end position of each video track of the magnetic tape, and the reproduced first and second vertical synchronization signals 1. A video signal recording and reproducing device characterized in that video signal processing is performed based on the video signal processing method.