JPS61102852A - Subsignal superrimposed system of cmi code - Google Patents

Abstract

PURPOSE:To superimpose more than one another signals and transmit by using unused '0' or '1' code regulation violation signal in a signal system used restric tively to a '0' or '1' code regulation violation of a frame bit. CONSTITUTION:A main signal inputting synchronously with a clock CLK enters a code mark inversion (CMI) coding circuit 5 and inputs a main signal '0' bit detecting circuit 2. When a frame signal C enters at a timing as shown in Fig. (c), thissignal is fed to the CMI coding circuit 5 as a polarity control signal of a code regulation violation (CRV), and a CRV signal is generated in the CMI coding circuit 5 and fed. In this case, there isrequired to control the polarity of the CRV signal for discriminating the CRV signal so as to meet ing a purpose, and a CRV enforcing control output is fed to the CMI coding circuit 5. A sub-signal (d) is inputted to a sub-signal synchronou circuit 1 and when as shown in Fig. (e), the main signal '0' bit detecting circuit detects a '0' signal, as shown in Fig. (f), a sub-signal superimposed position detecting circuit 3 drives a sub-signal superimposed circuit 4 to superimpose a sub-signal (f) on a frame output (g) as shown by a mark *.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to digital transmission using CMI codes,
In particular, the present invention relates to a CMI code sub-signal superimposition method that transmits information using a CMI code violation signal.

[Conventional technology]

CMI code (Code Mark Inversi)
on) is a code format that is often used in transmission between intra-office devices and communication using optical fibers. This code is B it sequence I n for information.
It is a binary code that takes into account the dependency (referred to as BS1), and is a code format that is widely used in optical communication equipment because it has good compatibility with optical communication.

Although the CMI code represents data “1”, the CMI code in Figure 6 (a
), the time between one time slot is expressed as a level, or 0 level, and to represent data "0", one time slot is divided into two, and the first half is expressed as 0 level, and the second half is expressed as level 0. vinegar.

Although there is a method of expressing the first half of a part as a level and the second half as an O level, it is not permitted, due to code rules, to have a method of expressing the first half as a θ level and a method of expressing the first half as a level in one system.

FIG. 6 1b) is an example of using CMI code, and the display data is "11010010101".

When communicating using the CMI code described above, frame signals are superimposed using code rule violations.

Generally, this code rule violation (hereinafter referred to as CRV)
(abbreviation for Violent) has a CRV of "1" and a CRV of "0", but for example, when using a CRV of "1", the transmitting side forcibly raises the CRV at the position of the frame pulse and transmits. However, on the receiving side, the frame signal is transmitted by constantly detecting CRV, and when detecting CRV, determining that a frame pulse exists at that position.

[Problem that the invention seeks to solve]

As explained above, when transmitting using CMI codes, a method has been used in which CRV is used to send frame signals, but the present invention utilizes CRV to further transmit one or more types of other signals. This is an attempt to provide a possible method.

[Means for solving problems]

The means to solve the problem is to set the frame bit to “1”.
In a signal system that is used only for violations of the sign rule of 0 or 0, an unused sign rule violation signal of 0 or 1 is used to superimpose one or more types of other signals. This is achieved by transmitting

[Effect]

According to the present invention, when using a CRV signal of "1" as a frame signal, it is noted that there is a very high possibility that a "0" signal always exists between one frame signal and the next frame signal, Depending on whether or not a "0" CRV signal is inserted between frame signals, a very large effect is produced in that one or more types of information other than the frame signal can be transmitted.

〔Example〕

FIG. 1 is a diagram illustrating the principle of a CMI code sub-signal superimposition method according to the present invention.

There is a gold input signal and a frame signal, and the frame signal has 1
Assume that a CRV of ° is used.

FIG. 1(a) shows an input data signal (the main system is in NRZ signal format), and FIG. 1 (bl indicates the frame signal position).

A CMI code signal corresponding to this case is shown in FIG. 1(C).

In this case, there is a high possibility that at least one "0" exists between one frame signal and the next frame signal. Assuming that there is always one “0”, this “0”
``Depending on whether the signal is a 0 CMI signal or a CRV signal, in other words, 0 within one frame interval''
It is possible to send information depending on the presence or absence of the CRV signal.

If there is a "0" signal at the position marked * in ta+ in Figure 1 (the * mark exists between the first frame pulse and the second frame pulse), the signal will be as shown in Figure 1 (j). A CRV signal of “0” is superimposed on the signal.

That is, whether there is a CRV signal of "0" in the first frame or not, whether there is a CRV signal of "0" in the second frame or not, and whether there is a CRV signal of "O" in the n-th frame. Since there is no frame signal, it is possible to send information different from the conventional frame signal.

Therefore, for example, there is a 0° CRV signal in the first frame (1), and there is no "O" CRV signal in the second frame (1).
0), there is a CRV signal of “0” in the nth frame (1
), it is possible to send the information 10...1.

Note that FIG. 1 (1) shows the case where there is no CRV signal of "0".

In this case, it is uncertain at which position within the frame the CRV signal is located, but as explained above, there is a very high possibility that one or more "0" will always exist, so the above signal superimposition method is realized. I can do it.

Further, in the present invention, it is necessary that no error signal is generated from the transmission path, and if there is an error signal, an error will occur in the superimposed signal.

FIG. 2 is a diagram showing an embodiment of a CMI code signal superimposition type transmitting side circuit according to the present invention.

FIG. 3 is a time chart of the transmitting circuit.

In the figure, 1 is a sub-signal synchronization circuit, 2 is a main signal "O" bit detection circuit, 3 is a sub-signal superimposition position detection circuit, 4 is a sub-signal superimposition circuit, and 5 is a CMI encoding circuit.

FIG. 3 (al indicates a clock CLK, and FIG. 3 fbl is a main signal input in synchronization with the clock CLK, and when it enters the CM1 encoding circuit 5, the main signal becomes "0".

input to the detection circuit 2. Main signal "0" Pino 1 moxibustion output circuit 2 constantly detects whether there is a "0" signal in the main signal.

When a frame signal is input at the timing shown in FIG. 3 (C1), this signal is sent to the CMI encoding circuit 5 as a CRV polarity control signal, and a CRV signal is generated and transmitted within the CMI encoding circuit 5.

In this case, CR is used to distinguish between frame signals and CRV signals.
It is necessary to control the polarity of the V signal to suit the purpose.
The CRV polarity control output is sent to the CMI encoding circuit 5.

When the sub signal is input to the sub signal synchronization circuit 1 as shown in FIG. 3 (dl) and the main signal "O" bit detection circuit 2 detects the "0" signal as shown in FIG. 3 tel, Figure 3(f)
As shown in FIG. 3, the sub-signal superimposition position detection circuit 3 drives the sub-signal superimposition circuit 4 to superimpose the sub-signal as shown by the * mark in FIG. 3 (gl).

FIG. 4 is a diagram showing an embodiment of a CMI code signal superimposition type receiving side circuit according to the present invention.

FIG. 5 is a time chart of the receiving side circuit.

In the figure, 6 is a CMI code decoding circuit, 7 is a sub-signal detection waveform modification circuit, and 8 is a delay circuit.

Data signal from CMI code decoding circuit 6 and "l"
The CRV signal is used as a frame signal in the main system (N
RZ signal), but the CRV signal of "0", that is, the sub signal, is detected by the sub signal detection waveform (1 and the positive circuit 7,
The waveform is corrected, and the delay circuit 8 uses the frame signal as a clock to align the rising or falling edges of the sub signals and output them.

CRV of “0” during the frame signal shown in Fig. 5 (al)
Although the signal is present, its position is indefinite as shown in FIGS.

In the above explanation, information was transmitted depending on whether or not one "0" CRV signal was inserted between frames, but the nth "0" signal between frames, 2n
It is also possible to send different information depending on whether or not there is a CRV signal in the th "0" signal and the 3nth "0" signal.

[Effects of the Invention] As described above in detail, the present invention has the great effect of being able to transmit one or more types of other signals in addition to the conventional frame signal transmission.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of a CMI code sub-signal superimposition method according to the present invention. FIG. 2 is a diagram showing an embodiment of a CMI code signal superimposition type transmitting side circuit according to the present invention. FIG. 3 is a time chart of the transmitting circuit. FIG. 4 is a diagram showing an embodiment of a CMI code signal superimposition type receiving side circuit according to the present invention. FIG. 5 is a time chart of the receiving side circuit. FIG. 6 is an explanatory diagram of CMI codes. In the figure, l is a sub-signal synchronization circuit, 2 is a main signal "0" bit detection circuit, 3 is a sub-signal superimposition position detection circuit, 4 is a sub-signal superimposition circuit, 5 is a CMI encoding circuit, and 6 is a CMI code decoding circuit. 7 is a sub-signal detection waveform correction circuit, and 8 is a delay circuit. Thickness 2 Figure 3

Claims (1)

[Claims] In a signal system that is used only when the frame bit is “1” or “0” in violation of the coding rule, “
A CMI code sub-signal superimposition method characterized by using a coding rule violation signal of "0" or "1" and superimposing and transmitting one or more types of other signals.