CA1256213A - Sub-information separating apparatus - Google Patents

Abstract

Abstract of the Disclosure A sub-information separating apparatus is arranged at a receiving side in a transmission system for sending a signal obtained such that a sub-information signal is superposed on a main signal by using coded mark inversion coding rule violation. The apparatus has a CMI
decoding converter, a pulse width stretching circuit and a sub-information separating circuit. The CMI decoding converter converts an input CMI signal to an original main signal and separates a CMI coding rule violation pulse from the input CMI signal. The pulse width stretching circuit stretches the pulse width of the CMI coding rule violation pulse. The sub-information separating circuit separates the sub-information signal from the pulse-width stretched CMI coding rule violation pulse.

Description

31.3 Specificatlon Title of the Invention Sub-Information Separating Apparatus Back round of the Invention The present invention relates to a sub-information signal separating circuit for separating a sub-inormation signal at a receiving side when the sub-information signal is superposed on a main signal by - 10 using CMI (Coded Mark Inversion) coding rule violation.
CMI coding is a coding scheme for glving redundancy to a digital signal to b~ transmitted. In CMI

~, .
coding, a one-bit input data signal is converted and coded to a 2-bit signal. For example, a binary "0" is converted to a binary "01". A binary "1" is converted to a binary "00" or "11" such that binary "00" and "11" alternate.
When the sub-information signal is superposed on the main ; signal at the sending side, CMI coding rule violation is intentionally effected by a superposed bit. For èxample, when a sub-information sign~l is superposed at a position of "0" in an input data signal, a corresponding output is set to be "10". However, when a sub-information signal is superposed at a position "1" in the input signal, alternating of "00" and "11" does not occur at this position, and the same output corresponding to the immediately preceding input signal "1" is generatedO

-:,' " - " . ,' '. , ~ , , '. ~ . - ', , .
: . :. .
, ;, .' ' '" '' ~' ' `' ':` ~ .

~ S~

In this case, at the receiving side, the CMI code "01" or "10" is converted to "0", and CMI code l00- or "11"
is converted "1", thereby reproducin~ the main signal indepenaently of the presence/absence of the sub-information signal. The sub-information signal can be detected and decoded by CMI co~ling rule violation. In general, the sub-information signal includes a plurality of types of sub-information compone~ts. After these components are decoded and separated into independent sub-information signals, conventional sub-information signal separation is performed at the same clock frequencv as in the main signal. Therefore, the sub-information signal separation circuit must be designed using high-speed elements corresponding to the bit rate of the main signal.
In particular, when the bit rate of the main signal is high, the power consumption is increased, and a temperature rise in equipment presents a critical problem. Further, when the number of sub-information signals to be superposed is large, the number and the cost of constituting components such as flip-flops is proportional to the number of sub-information signals.
Summary of the_Invention It is an object o~ the present invention to provide a ub-information separating apparatus wherein the low speed components are usable, allowing stable operation.
In order to achieve the above object of the present invention, there is provided a sub-information

- 2 - ~ ~

- - .
~` : ' :. - ' ~L~5~;2~1L3 separating apparatus arranged at a receiving side of a transmission system and adapted to decode main information and sub-information from a CMI signal and a main clock signal which are sent from a sending side, the CMI signal being obtained such that a plurality of types of ., sub-information co~ponents are superposed in accordance with coded mark inversion coding rule violation on a main signal derived by encoding the main information in accordance with coded mark inversion coding at a sending side, the main clock signal being adapted to correspond to the main signal, comprising: decoding converter circuit - means for receiving the CMI signal and the main clock signal, decoding the main signal and supplying a decoded `- main signal to a main signal output terminal, and generating the sub-information signal independently of the main signal; pulse width stretching circuit means for receiving the sub-information signal and the main clock signal from the decoding converter circuit means and stretching a pulse width of the sub-information signal; and ~- 20 sub-information separating circuit means for receiving a pulse-width stretched sub-information signal from the pulse width stretching circuit means and the main clock signal and supplying the sub-information components to corresponaing output terminalsu ~rief D cription of the Drawings Fig. 1 is a block diagram showing the overall :

. .

.

.

system configuration of a sub-information separating apparatus according to an embodiment of the present invention;
Fig. 2 is a represent:ation for explaining superposition of a sub-informat:ion signal on a main signal;
Figs. 3A to 3E are respectively timing charts of ; signals plotted along the common time base;
Fig. 4 is a circuit cliagram of a CMI decoding converter in Fig. l;
Fig. 5 is a circuit cliagram of a pulse stretching circuit in Fig. 1;
- Figs. 6A to 6F are timing charts for explaining the operation of the circuit in Fig~ 5;
Fig. 7 is a circuit diagram of a sub-information separating circuit in Fig. l; and Figs. 8A to 8E are respectively timing charts for explaining the circuit in Fig. 7.
Detailed Description of the Preferred Embodiment ; Fig. 1 is a block diagram showing the overall svstem configuration of a ub-information separating apparatu~ according to an embodiment of the present invention.
Referring to Fig. 1 and Fig. 2, a CMI signal Sl is supplied to an input terminal 1. The CMI signal S1 is obtained by superposing a sub-information signal on a main signal A at a rate of one information signal per n bits of the m~in signal A. In this case, the sub-information ':

.. . .
.

. .- . . :
.

: :
, ~L~5~ 1.3 components are given as Dl to D8. Normally, as shown in a format B in Fig. 2, sub-information components D1 to D8 are formatted into frames having frame signals F1, F2,... at the beginning, respectively. The sub-information components formatted in the frame in the manner described above are superposed on the bit positions of the main signal, indicated by the corresponding arrows. Figs. 3A to 3C are timing charts for explaining formation of the CMI
signal Sl. A main signal SM shown in Fig. 3A is coded in accordance with the above-mentioned CMI coding rule. A
sub-information signal S2 shown in Fig. 3B is superposed on the main signal ~M in accordance with CMI coding rule violation, thereby obtaining the CMI signal S1 shown in Fig. 3C. The CMI signal Sl from the input terminal 1 is supplied to a CMI decoding converter 3.
A clock signal CLK corresponding to the main signal SM is supplied to a terminal 2. The clock signal CLR is supplied to the CMI decoding converter 3, a pulse width stretching circuit, and a sub-information separating circuit 7.
The CMI decoding converter 3 decodes the CMI
signal Sl in response to the clock signal CLK. The decoded main signal SM is supplied to an output terminal 9. At the same time, CMI coding rule violation is detected, and thus the sub-information signal S2 is supplied to the pulse width stretching circuit 5 through a connecting line 4.

i .

2~

The pulse width stretching circuit 5 stretches the pulse width of the sub-information signal S2. A
pulse-width stretched signal S5 subjected to CMI coding rule vio].ation is supplied to t:he sub-information 5 separating circuit 7. The sub-information separating circuit 7 separates the sub-information components which are then respectively supplied to output terminals 8-1, 8-2,... 8-8.
Fig. 4 is a circuit diagram of the CMI decoding ;10 converter 3. The input terminal 1 is connected to input terminals D (to be referred to as D terminals hereinafter) of flip-flops (to be referred to as FFs hereinafter) 31 and 32. The clock input terminal 2 is connected to a clock input terminal T (to be referred to as a T terminal 15 hereinafter) of an FF 33. An output terminal Q (Q
terminal) of the FF 33 is connected to the D terminal : :
thereof and to the input terminal of a block synchronizing circuit 35. ~he output terminal of the block synchronizing circuit 35 is connected directly to the T terminal of the 20 FF 31 and to the T terminals of FFs 32 and 34 through an inverter 40. With these connections, the FFs 31, 32 and 34 receive the clock signals CLK31 and CLK32 respectively shown in Figs. 3D and 3E. The Q terminal of the FF 31 is connected to the D terminal of the FF 34. With this :
25 connection, the first bit of the 2-bit data signal of the CMI signal S1 is read by the FF 31, and the next bit is read by the FF 32. The FF 33 and the block synchronizing : . . "
: . ' ' : ' ' . ' ' :: - . . :

-. . ~ , , :

:~S~ 3 circuit 35 ad~ust the phases of the clock signals CLK31 and CLK32. The Q outputs from the FFs 34 and 32 are supplied to an exclusive NOR gate 36. The Q outpu~ from the FF 34 and the Q output from the FF 32 are supplied to an AND gate 5 37. The output terminal of the exclusive NOR gate 36 is connected to the output terminal 9 of the main signal. The output terminal of the AND gate 37 is connected to one input terminal of an OR gate 39. With this arrangement, the exclusive NOR gate 36 detects signals " 00 1l and "11" and generates a signal "1". Otherwise, the exclusive NOR gate 36 generates a signal "0". Therefore, the main signal SM
appears at the output terminal 9. The AND gate 37 detects "10" and generates a sianal "1". All outputs from the FFs 32 and 34 are supplied to a no~alternating detector 33.
When the nonalternating detector 38 detects nonalternating of "00" and "11", it supplies a signal "1" to the other input terminal of the OR gate 39. Therefore, when "10" is detected or nonalternating is detected, the output from the OR gate 39 is set at logic "1". Therefore, the sub-information signal S2 i5 sent onto the connectin~ line 4.
Fig. 5 is a circuit diagram of the pulse width stretching circuit 5. The connecting line 4 from the CMI
decoding converter 3 is connected to one input terminal of a NAND gate 51. The cloc~ input terminal 2 is connected to the other input terminal of the NAND gate 51. The terminal 2 is also connected to the T terminals of FFs 52 and 53.

-,, . - . , ................ ' :, . ~
- , , L.3 The Q terminal of the FF 52 is connected to the D terminal of the FF 53. The D terminal of the FF 52 is connected to the Q ter~inal o~ the FF 53, and a joint 56 thereof is connected to the T terminals of FFs 54 and 55. The D
5 terminal of the FF 54 is grounded, and the Q terminal thereof is connected to the D terminal of the FF 55. The set terminal S of the FF 54 is connected to the output terminal of the NAND gate 51. The Q terminal of the FF 55 is connected to the sub-information separating circuit 7 10 through a connecting line 6 (Fig. 1).
The operation of the pulse width stretching circuit 5 in Fig. 5 will be described with reference to the signal waveform timings (Figs. 6A to 6F) of the main part ~-~ of the circuit. The FFs 52 and 53 constitute a circuit for - 15 dividing the frequenc~ of the clock signal CLK to 1/4.
Therefore, a clock signal CLK50 in Fig. 6D appears at the joint 56. The clock signal CLR50 is supplied to the T
terminals of the FFs 54 and 55. The output from the NAND
gate 51, i.e., the signal S3 as a NANDed signal of the 20 sub-information signal S2 shown in Fig. 6A and the clock signal CLK in Fig. 6B is supplied to the set terminal S of the FF 54. Therefore, the FF 54 supplies from its Q
terminal to the D terminal of the FF 55 a signal S4 which rises at the trailing edge of the signal S3 and falls at - 25 the leading edge of the clock signal CLK50. Since the clock signal CLK50 is supplied to the FF 55, the FF 55 then generates from its Q terminal a signal S5 which rises at :
~ .
-, . . . ..

:
'. ~' '~ ~ . ' :
.~. . . .
~ ~ .
: . ..

~15~3~3 the trailing edge of the signal S4 and which ~alls at theleading edge of the clock signal CLK50. The signal S5 has a time slot four times that of the sub-information signal S2. The signal S5 is supplied to the sub-information separating circuit 7 through the connec~ing line 6.
Fig. 7 is a block diagram of the sub-information separating circuit 7, and Figs. 8A to 8E are timing charts of the signals thereof.
, Referring to Fig. 7, the connecting line 6 from the pulse width stretching circuit 5 is connected to a frame synchronizing circuit 71 and to the D terminals of : eight FFs 73-1, 73-2,... 73-8. The clock signal CLK from the clock input terminal 2 is supplied to the frame synchronizing circuit 71. The frame synchronizing circuit 71 generates clock signals CLKl, CLK2,...CLK8 for separating the sub-information components D1, D2,...D8 ~: included in the sub-information signal S5 in response to frame signals Fl, F2,... (Fig. 2~ included in the sub-information signal S5. The clocX signals CLKl, : 20 CLK2,... CLK8 are supplied to the T terminals of FFs 73-1, 73-2,73-8 through connecting lines 72-1, 72-2,72-8, respectively. The ~Fs 73-1 to 73-8 supply the ~ sub information components D1 to D8 from their Q terminals : to sub-information output terminals 8-1 to 8-8 in response to the clock signals CLKl to CLK8.
The timing relationship between the signals in Figs. 8A to $E is the same as the conventional circuit - _ g :
' without the pulse width stretching circuit 5. It should be noted that the pulse width of the suh-information signal S5 in this embodiment is four times that of the nonstretched sub-information signal S2, i.e., the bit rate of this 5 embodiment is 1/4. Therefore, the bit rate of the clock signals CLX1 to CLX8 is reduced to 1/4 of that of the conventional circuit. The FFs 73-1 to 73-8 and the frame synchronizing circuit 71 can be operated at a bit rate 1/4 that of the conventional circuit. As a result, the circuit 10 power consumption and hence cost can be decreased. In particular, when the number of sub-information signals to be superposed is large, this embodiment provides a great advantage.
Furthermore, when the stretching ratio 1/4 that 15 of the pulse width is set in accordance with the bit rate of the main signal, the sub-information separating circuit ~- 7 can be standardized irrespective of the bit rate of the main signal.

~- 20 . .
- :

.

Claims (3)

What is claimed is:

1. A sub-information separating apparatus arranged at a receiving side of a transmission system and adapted to decode main information and sub-information from a CMI
signal and a main clock signal which are sent from a sending side, the CMI signal being obtained such that a plurality of types of sub-information components are superposed in accordance with coded mark inversion coding rule violation on a main signal derived by encoding the main information in accordance with coded mark inversion coding at a sending side, the main clock signal being adapted to correspond to the main signal, comprising:
decoding converter circuit means for receiving the CMI signal and the main clock signal, decoding the main signal and supplying a decoded main signal to a main signal output terminal, and generating the sub-information signal independently of the main signal;
pulse width stretching circuit means for receiving the sub-information signal and the main clock signal from said decoding converter circuit means and stretching a pulse width of the sub-information signal; and sub-information separating circuit means for receiving a pulse-width stretched sub-information signal from said pulse width stretching circuit means and the main clock signal and supplying the sub-information components to corresponding output terminals.

2. An apparatus according to claim 1, wherein said pulse width stretching circuit means comprises frequency divider means for N-frequency dividing the main clock signal, and N-times stretching means for stretching the pulse width of the sub-information signal by N times in response to the clock signal from said frequency divider means.

3. An apparatus according to claim 1, wherein said pulse width stretching circuit means changes a stretching ratio of the pulse width in accordance with a bit rate of the main clock signal.