JPS6110234A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6110234A JPS6110234A JP13003384A JP13003384A JPS6110234A JP S6110234 A JPS6110234 A JP S6110234A JP 13003384 A JP13003384 A JP 13003384A JP 13003384 A JP13003384 A JP 13003384A JP S6110234 A JPS6110234 A JP S6110234A
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- spinel
- silicide
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、単結晶スピネル膜等の単結晶絶縁膜上にニ
ッケルシリサイド等の単結晶導電膜を形成して半導体装
置を作成する半導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor device in which a single crystal conductive film such as nickel silicide is formed on a single crystal insulating film such as a single crystal spinel film. Regarding the manufacturing method.
一般に、回路の高密度化、高集積化を図るためＫ、積層
構造の半導体立体回路素子の開発ンｆｉ進められており
、この場合、能動層が形成された半導体層および該半導
体層上に絶縁膜、配線用導電膜を順次積層していくが、
特性の優れた半導体立体回路素子を得るために、各材料
を単結晶状態のまま積層することが試みられている。In general, in order to increase the density and integration of circuits, the development of semiconductor three-dimensional circuit elements with a multilayer structure is progressing. Films and conductive films for wiring are sequentially laminated.
In order to obtain semiconductor three-dimensional circuit elements with excellent characteristics, attempts have been made to stack materials in a single crystal state.
そして、配線用導電膜として、たとえばエピタキシャル
シリサイド膜を形成することが考えられており、従来エ
ピタキシャルシリサイド膜であるニッケルシリサイド膜
を形成する方法として第１字ないし第３図に示すような
ものがある。It has been considered to form, for example, an epitaxial silicide film as a conductive film for wiring, and there are conventional methods for forming a nickel silicide film, which is an epitaxial silicide film, as shown in Figures 1 to 3. .
すなわち、第１図の方法は、たとえばシリコンソ・らな
る基板（１）上に、分子線エピタキシャル成長法（以下
ＭＢＥ という）により、ニッケルきすとシリコン（
ケイ素）〔Ｓ１〕とが１＝２の組成比になるようにして
単結晶のＮｉシリサイド膜（２）をエビタキンヤル成長
させるものである。That is, in the method shown in FIG. 1, nickel chips and silicon (
A single-crystal Ni silicide film (2) is grown in an epitaxial manner so that the composition ratio of silicon) [S1] is 1=2.
しかし、ＭＢＥ の場合、結晶成長速度が遅いため、Ｎ
１シリサイド膜（２）の形成のスループットが低く、実
用性にやや欠けるという欠点がある。However, in the case of MBE, the crystal growth rate is slow, so N
The disadvantage is that the throughput for forming the 1-silicide film (2) is low, making it somewhat impractical.
つぎに、第２図の方法は、シリコン基板（１）上にＮ１
を蒸着したのち、前記Ｎ１の蒸着膜に電気炉、うンプ加
郊等によるアニールを施こし、Ｎ１の拡散にＸり基板（
１）上に単結晶のＮ１シリサイド膜（３）を固相エピタ
キシャル成長させるものである。Next, in the method shown in Figure 2, N1 is placed on the silicon substrate (1).
After vapor-depositing N1, the N1 vapor-deposited film is annealed using an electric furnace, a pump, etc., and an X-ray substrate (
1) A single crystal N1 silicide film (3) is grown on it by solid phase epitaxial growth.
ところが、この方法を絶縁膜上のシリサイド形成に用い
る場合、Ｎ１蒸着膜の形成＠または形成後に８１を蒸着
しておく必要があるばかシか、アニール時に絶縁膜との
界面で相互拡散が生じてしまい、しかもエピタキシャル
成長しないという欠点がある。However, when this method is used to form silicide on an insulating film, it is necessary to evaporate 81 at or after the N1 deposition film is formed, or mutual diffusion occurs at the interface with the insulating film during annealing. Moreover, it has the disadvantage of not being able to grow epitaxially.
ざらに、第３図の方法は、シリコン基板（１）上ＫＮｉ
の蒸着によりＮ１蒸着膜（４）を形成したのち、イオン
注入法により、イオン化したＳＩｔなわちＳｒ をイ
オンエネルギ約＋００ ＫｅＶまで加速して蒸着膜（４
）に打ち込み、基板（１）上にＮ１シリサイド膜を形成
させるものである。Roughly speaking, the method shown in Figure 3 is based on the method shown in Fig. 3.
After forming the N1 vapor deposited film (4) by vapor deposition, the ionized SIt, that is, Sr, is accelerated to an ion energy of about +00 KeV by the ion implantation method to form the vapor deposited film (4).
) to form an N1 silicide film on the substrate (1).
しかしこの場合、前記した第１図、第２図の場合と異な
り、形成されたＮ１シリサイド膜は単結晶にならず、し
かも非常に高いイオンエネルギを持つＳ−の衝突により
、形成されたＮｉシリサイド膜に欠陥が生じるため、前
記したイオン注入法によφＮ１シリサイド膜により、半
導体立体回路素子の配線層を形成することができないと
いう欠点がある。However, in this case, unlike the cases shown in FIGS. 1 and 2 described above, the formed N1 silicide film does not become a single crystal, and moreover, due to the collision of S- with very high ion energy, the Ni silicide film formed Since defects occur in the film, there is a drawback that the wiring layer of the semiconductor three-dimensional circuit element cannot be formed using the φN1 silicide film by the above-described ion implantation method.
この発明は、前記の諸点に留意してなされたものであり
、半導体装置を作成する際のスループットの向上を図る
ことを目的とする。The present invention has been made with the above-mentioned points in mind, and an object of the present invention is to improve the throughput when manufacturing semiconductor devices.
この発明は、単結晶絶縁膜上に金属膜を蒸着し、イオン
エネルギ数ＫｅＶないし数１０ＫｅＶの半導体イオンを
イオン化蒸着法により前記金属膜に照射して前記絶縁膜
上に単結晶導電膜を形成し、前記絶縁膜および前記導電
膜からなる半導体装置を作成することを特徴とする半導
体装置の製造方法である。This invention involves depositing a metal film on a single crystal insulating film, and irradiating the metal film with semiconductor ions having an ion energy of several KeV to several tens of KeV by an ionization vapor deposition method to form a single crystal conductive film on the insulating film. , a method of manufacturing a semiconductor device, characterized in that a semiconductor device including the insulating film and the conductive film is manufactured.
したがって、この発明の半導体装置の製造方法によると
、蒸着した金属膜にイオンエネルギ数ＫｅＶないし数１
０ ＫｅＶのイオン化蒸着法により半導体イオンを照射
するため、イオンのミキシング効果により単結晶絶縁膜
上の全面にわたって単結晶導電膜を成長させることがで
き、しかも結晶成長速度がＭＢＥ の場合に比べて速い
ため、単結晶絶縁膜および単結晶導電膜からなる半導体
装置のスフレ−プツトの向上を図ることができるととも
に、イオンエネルギを数ＫｅＶないし数１０ＫｅＶにし
たため、イオン注入法の場合のように欠陥が発生すると
ともなく、特性の優れた半導体装置を作成する４ヒとが
でき４、単結晶からなる半導体立体回路素子の作成技術
として応用することが可能となり、非常に実用的である
。Therefore, according to the method of manufacturing a semiconductor device of the present invention, the ion energy of several KeV to several 1 is applied to the deposited metal film.
Since semiconductor ions are irradiated using the 0 KeV ionization vapor deposition method, it is possible to grow a single crystal conductive film over the entire surface of the single crystal insulating film due to the ion mixing effect, and the crystal growth rate is faster than in the case of MBE. As a result, it is possible to improve the swell of a semiconductor device made of a single-crystal insulating film and a single-crystal conductive film, and since the ion energy is set to several KeV to several tens of KeV, defects do not occur as in the case of ion implantation. As a result, it is possible to create a semiconductor device with excellent characteristics, and it can be applied as a technology for creating a semiconductor three-dimensional circuit element made of single crystal, which is very practical.
つぎに、この発明を、そのｌ実施例を示した第４図とと
もに詳細に説明する。Next, this invention will be explained in detail with reference to FIG. 4 showing an embodiment thereof.
まず、第４図（ａ）に示すような単結晶絶縁膜である単
結晶スピネル膜（５）を形成し、熱リン酸によりスピネ
ル膜（５）の表面をクリーニングしたのち、同図（ｂ）
に示すように、室温、高真空下でスピネル膜（５）上に
蒸着により金属膜である厚さ約１０００ ＸのＮ１蒸着
膜（６）を形成する。First, a single crystal spinel film (5) which is a single crystal insulating film as shown in FIG. 4(a) is formed, and after cleaning the surface of the spinel film (5) with hot phosphoric acid, as shown in FIG. 4(b).
As shown in FIG. 2, an N1 vapor-deposited film (6) having a thickness of approximately 1000× is formed as a metal film by vapor deposition on the spinel film (5) at room temperature and under high vacuum.
つぎに、Ｓｒをイオン化率数％にイオン化し、膜（５）
、 （６１の温度を適当な温度に保ちつつ、イオン化
蒸着法により、第４図（Ｃ）に示すように、イオン化し
たシリコンすなわちＳｌ をイオンエネルギ約５Ｋｅ
Ｖまで加速してＮ１蒸着膜（６）の全面に照射すると、
８＋ のミキシング効果により、スピネル膜（５）上
の全面にわたってＮ１シリサイド（ＮｉＳｉ２）がエピ
タキシャル成長し、スピネル膜（５）上に同図（ｄ）
Ｋ示すような単結晶導電膜である単結晶のＮ１シリサイ
ド膜（７）が形成され、スピネル膜（５）とＮ１シリサ
イド膜（７）１に）らなる半導体装置（８）が作成され
る。Next, Sr is ionized to an ionization rate of several percent, and the film (5) is formed.
(While keeping the temperature of 61 at an appropriate temperature, ionized silicon, ie, Sl, is heated to an ion energy of approximately 5Ke by ionization vapor deposition as shown in FIG. 4(C).
When accelerated to V and irradiated to the entire surface of the N1 vapor deposited film (6),
Due to the mixing effect of 8+, N1 silicide (NiSi2) is epitaxially grown over the entire surface of the spinel film (5), and as shown in the figure (d) on the spinel film (5).
A single-crystal N1 silicide film (7), which is a single-crystal conductive film, as shown in FIG.
なお、このときの結晶成長速度は約１０００〜−であり
、Ｎｉシリサイド膜（７）の形成後のＮｉと８１との組
成比が１＝２となるようにしている。Note that the crystal growth rate at this time is about 1000 to -, and the composition ratio of Ni and 81 after the formation of the Ni silicide film (7) is set to 1=2.
そして、このようにして形成された半導体装置（８）を
能動領域が形成されたシリコン基板上にｉ層して配線用
導電層とし、さらに積層し７’（Ｎｉシリサイド膜（７
）上に単結晶スピネル膜等の単結晶層間絶縁膜を介在し
て次層の基板を積層し、これらを繰シ返すことにより、
単結晶層・らなる特性の優れた半導体立体回路素子を形
成することができる。Then, the semiconductor device (8) thus formed is formed into an i-layer on a silicon substrate on which an active region is formed to serve as a conductive layer for wiring, and is further laminated to form a layer 7' (Ni silicide film (7)).
), by stacking the next layer of substrate with a single crystal interlayer insulating film such as a single crystal spinel film interposed therebetween, and repeating these steps,
It is possible to form a semiconductor three-dimensional circuit element with excellent characteristics consisting of a single crystal layer.
したがって、前記実施例によると、イオンのミキシング
効果によりスピネル膜（５）の全面にわたってＮｉシリ
サイド膜（７）をエピタキシャル成長させることができ
、しかもＮ１シリサイド膜（７）の結晶成長速度がＭ
Ｂ Ｅに比べ約１０倍速くなるため、半導体装置（８）
のスループツトの向上を図ることができる。Therefore, according to the embodiment, the Ni silicide film (7) can be epitaxially grown over the entire surface of the spinel film (5) due to the ion mixing effect, and the crystal growth rate of the N1 silicide film (7) is M
BE is about 10 times faster than E, so semiconductor devices (8)
Throughput can be improved.
ｉ ｆｔ、Ｓ＋ のイオン化蒸着におけるイオンエキ
１ギを数ＫｅＶないし数１０ＫｅＶにしたため、イオン
１電入法の場合のように欠陥が発生することもなく、特
性の優れた半導体装置（８）を作成することができる。Since the ion energy in the ionized vapor deposition of i ft, S+ is set to several KeV to several tens of KeV, a semiconductor device (8) with excellent characteristics is produced without defects unlike in the case of the single ion deposition method. be able to.
さらに、この半導体装置（８）を半導体立体回路素子の
各配線用導電層に適用することによシ、単結晶からなる
特性の優れた半導体立体回路素子を容易に提供すること
ができ、非常に実用的′である。Furthermore, by applying this semiconductor device (8) to each conductive layer for wiring of a semiconductor three-dimensional circuit element, it is possible to easily provide a semiconductor three-dimensional circuit element with excellent characteristics made of a single crystal, which is very effective. It is practical.
しかも、Ｎ１蒸着膜（６）をイオン化蒸着の前に形成し
たため、Ｓｌ によるチャージアップを防止すること
ができ、イオンのミキシング効果を有効に高めることか
できる。Moreover, since the N1 vapor deposition film (6) is formed before ionization vapor deposition, charge-up due to Sl 2 can be prevented, and the ion mixing effect can be effectively enhanced.
なお、単結晶絶縁膜としてスピネル膜（５）以外に、サ
ファイヤ、フッ化カルシウム（ＣａＦ２）等の単結晶膜
を使用しても、さらに金属膜としてＮ１以外にコ／＜／
Ｌ／ ｌ−、ハラジウム、白金を使用しても、この発明
を同様に実施することができる。Note that even if a single crystal film of sapphire, calcium fluoride (CaF2), etc. is used in addition to the spinel film (5) as the single crystal insulating film, it is possible to use a single crystal film other than N1 as the metal film.
The invention can be practiced similarly using L/1-, haladium, and platinum.
第１図ないし第３図はそれぞれ従来のＮ１シリサイド膜
の形成過程を示す断面図、第４図（１１）〜（ｄ）はこ
の発明の半導体装置の製造方法の１実施例を示し、製造
過程を示す断面図である。
（５）・・・単結晶スピネル膜、（６）・・・Ｎｉ蒸着
膜、（７）・・・Ｎ１シリサイド膜、（８）・・・半導
体装置。
特許出願人 工業技術院長 川 １）裕 部０（
２） ■
第４図1 to 3 are cross-sectional views showing the conventional N1 silicide film formation process, and FIGS. 4(11) to 4(d) show an embodiment of the method for manufacturing a semiconductor device of the present invention, and the manufacturing process FIG. (5)...Single crystal spinel film, (6)...Ni vapor deposited film, (7)...N1 silicide film, (8)...Semiconductor device. Patent applicant: Director of the Agency of Industrial Science and Technology Kawa 1) Yube 0 (
2) ■ Figure 4
Claims (1)
数ＫｅＶないし数１０ＫｅＶの半導体イオンをイオン化
蒸着法により前記金属膜に照射して前記絶縁膜上に単結
晶導電膜を形成し、前記絶縁膜および前記導電膜からな
る半導体装置を作成することを特徴とする半導体装置の
製造方法。1. A metal film is deposited on a single crystal insulating film, and the metal film is irradiated with semiconductor ions having an ion energy of several KeV to several tens of KeV by an ionization vapor deposition method to form a single crystal conductive film on the insulating film. 1. A method for manufacturing a semiconductor device, comprising the steps of: manufacturing a semiconductor device comprising a film and the conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13003384A JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13003384A JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6110234A true JPS6110234A (en) | 1986-01-17 |
| JPH038103B2 JPH038103B2 (en) | 1991-02-05 |
Family
ID=15024483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13003384A Granted JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110234A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4262726B2 (en) | 2005-08-24 | 2009-05-13 | 任天堂株式会社 | Game controller and game system |
-
1984
- 1984-06-26 JP JP13003384A patent/JPS6110234A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH038103B2 (en) | 1991-02-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |