JPS61100842A - Scanning circuit - Google Patents

Scanning circuit

Info

Publication number
JPS61100842A
JPS61100842A JP59221311A JP22131184A JPS61100842A JP S61100842 A JPS61100842 A JP S61100842A JP 59221311 A JP59221311 A JP 59221311A JP 22131184 A JP22131184 A JP 22131184A JP S61100842 A JPS61100842 A JP S61100842A
Authority
JP
Japan
Prior art keywords
scan
circuit
scanning circuit
state memory
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59221311A
Other languages
Japanese (ja)
Inventor
Akimitsu Tateishi
立石　昭光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59221311A priority Critical patent/JPS61100842A/en
Publication of JPS61100842A publication Critical patent/JPS61100842A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Abstract

PURPOSE:To suppress increase in number of terminal to the minimum so that only necessary circuits can be tested, by performing scan-in and scan-out to an optional state storing circuit group. CONSTITUTION:In order to operate the scanning circuit shown in the figure as an ordinary scanning circuit, an enable signal T, scan-in signal line 2 which is set to an independent mode at '0', and scan-out signal line 7 are turned off by respective transfer gates 4 and 9. Simultaneously, the inverted signal T of the enable signal becomes '1' and the scan-pass 1 from the previous step or scan-pass 8 to the next step is turned on, and then, a state storing circuit group 6, in which several state storing circuits 5 are aggregated, operates as a part of an ordinary scanning circuit. When the circuit is operated as an independent scanning circuit, the enable signal T is set at '1' and the signal lines 2 and 7 are turned on by means of the gates 4 and 9.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は論理装置の診断を効率的にする為の論理装置の
設計法に係わり、特に論理装置の状態記憶回路の一部に
スキャンイン／アウトを行うことができる様に構成し九
論理装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of designing a logic device for efficient diagnosis of the logic device, and particularly to a method for designing a logic device in which a part of the state storage circuit of the logic device is scan-in/out. This invention relates to nine logic devices configured to be able to perform the following operations.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路技術の発展に伴い、集積回路の入出力ピ
ン数の制限から、その論理装置の良否の判定及び故障部
分の解析に要するテストデータの作成が極めて困難にな
るが、スキャン方式は少ない入出力ピン数で論理試験を
行う方法として有力な手段であることが知られている．
論理装置が故障して異常動作を起こしている場合にその
原因を知る手段として、外部から直接論理装置の状態を
設定し、動作させ、動作後の状態を知ることにより、故
障の原因を判定するものである。With the development of semiconductor integrated circuit technology, it has become extremely difficult to create the test data required to determine the pass/fail of logic devices and analyze faulty parts due to the limited number of input/output pins of integrated circuits. It is known to be an effective method for performing logic tests based on the number of output pins.
When a logical device is malfunctioning and operating abnormally, this method is used to determine the cause of the failure by directly setting the logical device's state from the outside, operating it, and knowing the state after operation. It is something.

従来のスキャン方式は、第４図に示す様な構成であり、
スキャンイン信号線から入力されたスキャンデータは、
状態記憶回路の果合１１ないし１４にセットされ１５の
内部論理回路を動作させ、その動作〈よって１１ないし
１４にセットされた出力レータをスキャンアウト信号線
より出力し、結果を期待値と比較するものである。The conventional scanning method has a configuration as shown in Figure 4.
The scan data input from the scan-in signal line is
The results of the state memory circuit are set to 11 to 14 to operate 15 internal logic circuits, and the output ratio set to 11 to 14 is output from the scan-out signal line and the result is compared with the expected value. It is something.

しかしながら、この方法では、状態記憶回路の内一部を
見たい時でも、同期信号を全状態記憶回路の個数分入力
してスキャンイン・スキャンアウトを行う必要があり、
その個数が多い場合、スキャンイン・スキャンアウトに
多大の時間を費す危険性がある。However, with this method, even when you want to see a part of the state memory circuits, it is necessary to input synchronization signals for all state memory circuits and perform scan-in/scan-out.
If the number is large, there is a risk that a large amount of time will be spent on scan-in and scan-out.

〔発明の目的〕[Purpose of the invention]

本発明は、上述した従来装置の欠点を改良したもので、
任意の状態記憶回路群に対し、スキャンイン−スキャン
アウトを行うことができ、通常のスキャンイン・スキャ
ンアウトも行うことができるスキャン回路装置を提供す
ることを目的とする。The present invention improves the drawbacks of the conventional device described above.
It is an object of the present invention to provide a scan circuit device that can perform scan-in and scan-out for an arbitrary state storage circuit group, and can also perform normal scan-in and scan-out.

〔発明の概要〕[Summary of the invention]

以下、本発明の概要を図面を用いて説明を行う。 Hereinafter, an outline of the present invention will be explained using the drawings.

第１図は、本発明のスキャン回路を示したものである。FIG. 1 shows a scan circuit of the present invention.

この回路を通常のスキャン回路として動作させ９るには
、まずエネイブル信号Ｔｔ−”０”にして独立モードの
スキャンイン信号線２、独立モートノスキャンアウト信
号線７を各々のトランスファーゲート４、あるいは９に
よってＯＦＰ　Ｋする。同時にエネイブル信号の反転信
号Ｔは一１〃となり前段からのスキャンバス１あるいは
次段へのスキャンパス８はＯＮになり、状態記憶回路５
をいくつかよせ集めた状態記憶回路群６は、通常のスキ
ャン回路の一部として動作する。To operate this circuit as a normal scan circuit, first set the enable signal Tt to "0" and connect the independent mode scan-in signal line 2 and independent mode scan-out signal line 7 to each transfer gate 4 or OFPK by 9. At the same time, the inverted signal T of the enable signal becomes 11, and the scan path 1 from the previous stage or the scan path 8 to the next stage is turned ON, and the state storage circuit 5
The state memory circuit group 6, which is a collection of several state memory circuits, operates as a part of a normal scan circuit.

この回路を独立のスキャン回路として動作させるには、
まず、エネイブル信号Ｔを気１〃にして独立モードのス
キャイン信号線２、独立モードのスキャンアウト信号線
７を各々のトランスファーゲート４、あるいは９によっ
てＯＮにする。同時に、エネイブル信号の反転信号Ｔは
気Ｏ〃となり、前段からのスキャンバス１あるいは、次
段へのスキャンパス８はＯＦＦになり、状態記憶回路群
６は独立したスキャン回路として動作する。To operate this circuit as an independent scan circuit,
First, the enable signal T is set to 1, and the independent mode scan-in signal line 2 and the independent mode scan-out signal line 7 are turned on by each transfer gate 4 or 9. At the same time, the inverted signal T of the enable signal becomes O, the scan path 1 from the previous stage or the scan path 8 to the next stage is turned off, and the state storage circuit group 6 operates as an independent scan circuit.

〔発明の効果〕〔Effect of the invention〕

本装置により、スキャン回路中必要な部分のみのテスト
が端子数の増加を最小限に抑えて行うことができ、テス
ト時間を短縮することができる。With this device, only the necessary portions of the scan circuit can be tested while minimizing the increase in the number of terminals, and the test time can be shortened.

又、必要に応じて従来通りのスキャン動作もできる。Furthermore, conventional scanning operations can be performed if necessary.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面を用いて詳細に説明する
。Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

第２図は、本発明のスキャン回路を組み込んだ実施例で
ある。スキャン用状態記憶回路は１１ないし１４０部分
で、独立にデータをスキャンイン・スキャンアウトでき
るようになっている。１７ないし２７はトランスファー
ゲートで、エネイブル信号Ｔ１ないしＴｎ、又、その反
転信号Ｔ１ないしＴｎによってスキャン動作が独立か、
そうでないかが選択される。さらにスキャンインデータ
はデマルチプレクサ２８によってスキャンされるべき状
態記憶回路群にデータセレクト信号によって入力される
。FIG. 2 shows an embodiment incorporating the scan circuit of the present invention. The scan state storage circuit has sections 11 to 140 that can independently scan in and scan out data. Reference numerals 17 to 27 designate transfer gates, and scan operations are performed independently by enable signals T1 to Tn or their inverted signals T1 to Tn.
Otherwise, it is selected. Furthermore, the scan-in data is input by the data select signal to the state storage circuit group to be scanned by the demultiplexer 28.

スキャンアウトデータも、マルチプレクサ２９によって
、データセレクト信号で選択され、出力される。The scan-out data is also selected by the multiplexer 29 using a data select signal and output.

又、第３図は、エネイブル信号の出力方法の一例を示し
たものである。エンコーダ３０によりデータセレクト信
号はパラレルに：Ｔ１ないしＴｎにわりふられ、各状態
記憶回路群の動作を決定する。Further, FIG. 3 shows an example of a method of outputting an enable signal. The encoder 30 distributes the data select signals in parallel: T1 to Tn to determine the operation of each state storage circuit group.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の概略を示すスキャン回路の回路図、第
２図は本発明の一実施例の回路図、第３図はエネイブル
信号分配回路の回路図、第４図はスキャン回路の従来例
の回路図である。 図において。 ｌ・・・前段からのスキャンバス、 ２・・・独立モードのスキャンイン、 ３．４・・・トランスファーゲート、 ５・・・状態記憶回路、 ６・・・状態記憶回路群、 ７・・・独立モードのスキャンアウト、８・・・次段へ
のスキャンパス。 ９．１０・・・トランスファーゲート、１１〜１４・・
・状態記憶回路群、 １５・・・内部論理回路、 １６〜２７・・・トランスファーゲート、２８・・・デ
マルチプレクサ、 ２９・・・マルチプレクサ、 ３０・・・エンコーダ 代理人　弁理士　則近憲佑　（他１名）第　　２　図 第　　３　図 第４図Fig. 1 is a circuit diagram of a scan circuit showing an outline of the present invention, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a circuit diagram of an enable signal distribution circuit, and Fig. 4 is a conventional scan circuit. FIG. 3 is an example circuit diagram. In fig. 1... Scan canvas from previous stage, 2... Scan-in in independent mode, 3.4... Transfer gate, 5... State memory circuit, 6... State memory circuit group, 7... Independent mode scan out, 8...Scan path to next stage. 9.10...Transfer gate, 11-14...
- State memory circuit group, 15... Internal logic circuit, 16-27... Transfer gate, 28... Demultiplexer, 29... Multiplexer, 30... Encoder agent Patent attorney Kensuke Norichika ( 1 other person) Figure 2 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）論理回路の状態記憶回路をシフトレジスタチェー
ンに構成して、テストデータのスキャンイン／アウトを
可能にした論理装置において、状態記憶回路の集合を外
部から任意に選択し、その集合に対してのみ、スキャン
イン／アウトを行い、他の状態記憶回路の内容を破壊し
ない様に構成したことを特徴とするスキャン回路。(1) In a logic device in which the state memory circuits of the logic circuit are configured into a shift register chain to enable scan-in/out of test data, a set of state memory circuits is arbitrarily selected from the outside, and the set of state memory circuits is What is claimed is: 1. A scan circuit characterized in that the scan circuit performs scan-in/out only when the state memory circuit is in use, and is configured so as not to destroy the contents of other state memory circuits. （２）特定の集合に対するスキャンイン／アウトの他に
、通常の全状態記憶回路に対するスキャンイン／アウト
も行える様に構成したことを特徴とする前記特許請求の
範囲第１項記載のスキャン回路。(2) The scan circuit according to claim 1, characterized in that the scan circuit is configured to be able to perform scan-in/out for a general all-state storage circuit in addition to scan-in/out for a specific set.
JP59221311A 1984-10-23 1984-10-23 Scanning circuit Pending JPS61100842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59221311A JPS61100842A (en) 1984-10-23 1984-10-23 Scanning circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59221311A JPS61100842A (en) 1984-10-23 1984-10-23 Scanning circuit

Publications (1)

Publication Number Publication Date
JPS61100842A true JPS61100842A (en) 1986-05-19

Family

ID=16764807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59221311A Pending JPS61100842A (en) 1984-10-23 1984-10-23 Scanning circuit

Country Status (1)

Country Link
JP (1) JPS61100842A (en)

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