JPS6097759A - Demodulator - Google Patents

Abstract

PURPOSE:To obtain directly original data with simple circuit constitution by gating a mudulation signal whose phase is controlled in response to a data difference signal for a prescribed period at adjacent data transmission periods and integrating the gated result. CONSTITUTION:A modulation signal (DPSK signal) whose phase is controlled in response to a data difference signal is gated for a prescribed period at a gate circuit 12. The timing of the gate is decided by a timing circuit 16 in response to a horizontal synchronizing signal. After the DPSK signal gated by the gate circuit 12 is integrated at an integration device 13, the result is fed to a comparator 18 via a peak hold circuit 17. The comparator 18 compares an output of the integration device 13 before one bit data transmission period held in the hold circuit 17 with an output of the integration device 13 at present and the DPSK signal is demodulated.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a demodulation device, and particularly to a demodulation device for demodulating a modulation signal whose phase is controlled according to a data difference signal, so-called DPSK (Differential
tial Phase 5hift Keying)
The present invention relates to a device for demodulating a signal.

<Description of Prior Art> Hereinafter, in this specification, DPS synchronized with a video signal
The K signal will be explained. Figure 1 is a diagram for explaining a DPSK signal synchronized with a video signal.
) indicates the original data, for example, 4 as shown in the figure.
It is assumed that 1 bit of data is included in the horizontal scanning period (H). Figure 1 (1,) is the difference signal of data (a); when data (a) is 0, the difference signal is the same as the previous value, and when it is 1, it is inverted from the previous value. (0) is a video signal, and (d) is a DPSK signal.Also, as is clear from the time-enlarged diagram on the right side of Figure 1, the DPSK signal (
In d), the frequency is the same when the difference signal (b) is 1 and when it is 0, but the phase is reversed. Now, the DPSK signal (d
) is assumed to have a predetermined phase relationship with the horizontal synchronizing signal of the video signal (c).

Conventionally, this type of DPSK signal has been demodulated using a circuit as shown in FIG. 2, for example. In Figure 2, 1 is the terminal to which the DPSK signal is input, 2 is the terminal 1
A phase quadruple loop (PL) outputs a signal that is in phase with the input DPSK signal and has twice the frequency.
L) circuit, 6 is a 1/2 frequency divider, 4 is a comparator that compares the DPSK signal input to terminal 1 and the output signal of the frequency divider.
5 is a demodulator, and 6 is an output terminal for reproduced data.

Figures 6(a) to (θ) are timing charts showing the waveforms of each part of Figures 2(a) to (θ).As is clear from Figure 6(C), the 1/2 frequency divider The output signal has the same frequency as the input DPSK signal and the phase is always constant. 0 Comparator 4 outputs a high level output when the phase difference between the two input signals is 180°. 0 Therefore, the output of comparator 4 is DP
The 0 demodulator 5, which becomes a no-y level only when the SK signal is inverted and becomes a differential signal of the original data, changes this ratio I every 4H, that is, every period in which 1 bit of data is transmitted
I! The output data of the 12 unit 4 is sampled, and when the sampling output is at the NO level, the output data is inverted. Therefore, the original data can be obtained from the demodulator 5. However, the above-mentioned configuration When demodulating with
Since the original data is demodulated after a data difference signal is obtained, the circuit configuration becomes complicated. Furthermore, it is necessary to prepare one PLL circuit, a frequency divider, etc., and there is a problem that the scale of the circuit inevitably becomes large.<Object of the Invention> The present invention was made in view of the above-mentioned drawbacks. Therefore, it is an object of the present invention to provide a demodulator that can directly obtain original data from a DPSK signal with an extremely simple circuit configuration.

<Explanation based on examples> The present invention will be explained below using examples.

FIG. 4 is a diagram showing a demodulating device for DPSK signals as an embodiment of the present invention, and FIG.
Figures (a) to (1) below are waveform diagrams showing waveforms of various parts.Operations will be explained based on these figures.

In Fig. 4, the DPSK signal input from terminal 11 (
a) is gated by the gate circuit 12 for a predetermined period.

The gate timing is determined by the horizontal synchronization signal (1) separated by the synchronization separation circuit 15 from the video signal input from the terminal 14.
) is determined by the timing circuit 16 according to the timing. FIG. 5(C) shows a gate control signal generated by the timing circuit 16. When one bit of data is transmitted in 4H, one gate control signal is generated in 4H. The gate control signal (C) has a predetermined phase difference with respect to the horizontal synchronization signal (b), and has a phase difference of τ! shown in FIG. is constant), and its gate period is constant (τ2 shown in FIG. 5 is constant).

By the way, depending on how 1 and τ2 are selected, the comparison described later may not be possible. Therefore, for τ1, the rising edge of the gate control signal (C) is DPSK.
It is desirable that the signal does not fall or rise, and it is desirable that τ2 not be an integral multiple of τD. However, τ1. Regarding τ2, if one of them satisfies the above-mentioned conditions, it is definitely possible to perform the comparison operation described later.

The DPSK signal (d) gated by the gate circuit 12 is supplied to the integrator 16. The output of the integrator 16 is supplied to a hold circuit 17 and a comparator 18. and the output of the current integrator 16 are compared. The timing of this comparison is performed after the gate by the gate circuit 12 is completed and before the hold by the hold circuit 17,
A signal (h) for controlling this timing is also obtained from the timing circuit 16.

Now, if the phase of the DPSK signal is inverted in the previous and subsequent data transmission periods, the average levels in these periods are different. In other words, in this case, the DPSK signal could be demodulated by creating a difference in the output of the integrator 16 and outputting 0 when the two inputs are equal.

When the comparison by the comparator 18 is completed, the current output of the integrator 16 is held in the hold circuit 17 in preparation for the next comparison.

As explained above, the value obtained by dividing the DPSK signal by gated for a predetermined period in adjacent data transmission periods changes only when the phase of the DPSK signal can change.

Therefore, according to the above-mentioned configuration, there is no need to create a signal whose phase matches that of the DPSK signal, and there is no need to temporarily set the difference signal, so that the DPSK signal can be tuned with a simple circuit configuration of m1.

FIG. 6 is a diagram showing a DPSK signal demodulation device as another embodiment of the present invention. Components in Figure 6 that are similar to those in Figure 4 are designated by the same numbers.0 In Figure 6, 21
is an analog-to-digital converter (A/D converter), 22
is a latch circuit 0 In this example, as shown in the figure, the output of the integrator 16 is A/D converted by an A/D converter 21 to form a latch circuit 2.
The latch circuit 22 latches the output of the A/D converter 21 after the comparison by the comparator 18 is completed. As a result, the comparator 18 compares the integrated value of the DPSK signal for a predetermined period in the data transmission period of adjacent 1 bit, as in the previous embodiment, and the DPSK signal can be demodulated.

Figure 2C47 shows a DPSK as yet another embodiment of the present invention.
FIG. 3 is a diagram illustrating a signal rhythmic device. Components in FIG. 7 that are similar to those in FIG. 6 are given the same numbers. Also the 8th
The figure is a timing chart showing the waveforms of each part in FIGS. 7(a) to (k).

In Figure 7, 61 is an up/down counter, and 62 is D.
A terminal to which a clock having a frequency sufficiently higher than that of the PSK signal is input, is a gate circuit that gates the clock input from the terminal J' 32 and supplies it to the counter 61. In this configuration, the DPSK signal (i) is supplied to the up/down control input of the counter 61, so the output of the counter 1 is proportional to the average level of the DPSK signal during a predetermined period during the data transmission period. This is supplied to the latch circuit 22 and the comparator 18.The comparator 18 demodulates the DPSK signal by comparing the outputs of the counter 61 in adjacent data transmission periods, as in the previous embodiment. The counter 61 is reset by a reset pulse (shown in FIG. 8(f)) obtained from the timing circuit 16 after the comparison by the ratio φ calculator 18 and the latching by the latch circuit 22 are completed.

Even with the above configuration, the output of the counter 31 is proportional to the average level of the DPSK signal within the predetermined period mentioned above, so the output of the comparator 18 is proportional to the D
This means that the PSK signal has been demodulated.It is desirable that the frequency of the clock input to the counter 61 is sufficiently higher than the frequency of the DPSK signal.

In addition, in the above embodiment, the DP of the period specified by the gate
Although an integrator, an up/down counter, etc. are used as means for obtaining information corresponding to the average level of the SK signal, it is of course possible to use other circuits.

<Description of Effects> As explained above, according to the present invention, the PLL circuit is similar to a PLL circuit.
There is no need for a means to obtain a signal synchronized with the SK signal,
Furthermore, since there is no need to perform processing to obtain a differential signal once, it has become possible to demodulate a DPSK signal with a much simpler circuit configuration than conventional demodulators.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining the DPSK signal, Fig. 2 is a diagram showing the circuit configuration of a conventional DPSK signal demodulation device, Fig. 3 is a timing chart showing the waveform of the section in Fig. 2, and Fig. 4 5 is a timing chart showing the waveform of the section shown in FIG. 4, and FIG. 6 is a diagram showing a DPSK signal demodulation device as an embodiment of the present invention. FIG. 7 is a diagram showing a demodulator for a DPSK signal as yet another embodiment of the present invention. FIG. 8 is a timing chart showing the waveform of the seventh section. 11 is a DPSK signal input terminal, 12 is a gate circuit as a specifying means, 16 is an integrator, 15 is a synchronous separation circuit, 1
6 is a timing circuit, 17 is a hold circuit, 18 is a comparator, 21 is an A/D converter, 22 is a latch circuit, 61 is a counter, and 6 is a gate circuit as a specifying means.

Claims (1)

[Claims] 1) A device for demodulating a modulated signal whose phase is controlled according to a data difference signal, comprising means for specifying a predetermined period for each data transmission period, and a period not specified by the specifying means. A demodulating device comprising: means for obtaining information corresponding to the average level of the modulated signal; and means for comparing the information corresponding to the predetermined period in the adjacent transmission periods.