JPS6083425A - Demodulating circuit - Google Patents

Abstract

PURPOSE:To obtain a proper clock signal from a digitally modulated signal by providing a clock generating circuit, phase decision circuit, and clock phase inverting circuit. CONSTITUTION:A decision window signal (f) is inputted from a clock phase decision window detecting circuit 51 to the clock phase decision circuit 54 to decide on whether a digital signal (g) is 0 or 1 when the signal (f) is at a level 1. The circuit 54 decides that the phase of a synchronizing clock signal (j) used by demodulating circuit 52 for demodulation is not proper when the digital signal (g) is 1, and outputs a phase inversion signal (h) to the clock phase inverting circuit 55. On receiving the phase inversion signal (h), the circuit 5 inverts the phase of the synchronizing clock signal (j) being inputted from a frequency dividing circuit 56 to correct the phase of the clock. Therefore, a synchronizing clock (i) applied to the demodulating circuit 52 has the proper phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a demodulation circuit for demodulating digitally modulated signals used for digital signal transmission, image electronic files, and the like.

[Prior art]

For example, MFM modulation (Modified Frequency Modulation) that digitally modulates a digital signal
ation ) is used in floppy disk devices and the like.

The demodulation of the MFM signal will be briefly described below.

When performing MFM modulation on a digital signal of 0 or 1, as shown in Figure 1 (1) and (2), the 0, 1 of the digital signal (1) to be modulated (each unit is called a bit cell). On the other hand, when the data is 1, the modulated signal (2) is inverted at the center of the bit cell, and when the data is O, it is inverted at the boundary of the bit cell only when two or more consecutive 0s occur. When demodulating this MFM signal, it is necessary to judge whether the changing point of the MFM signal is at the center or the boundary of the bit cell. It is necessary to have a phase that can be identified.

For this reason, floppy disk devices and the like have conventionally used a 2-use long loop (hereinafter referred to as P, L, L) as a clock generator, and as shown in Figure 2, the MFM signal (1) is , set some kind of 1ltJI pattern A (for example, a series of 0s as data),
As shown in Fig. 2 (2), each setter B pulls in P, L, L in this synchronization pattern part A, obtains a clock synchronized with synchronization pattern A, and after the synchronization pattern ends and enters the data area. , and is configured to output a clock signal with the same phase. Note that C is a gap area between signals.

This type of configuration is good for applications where the demodulated signal is simply treated as data, but when it is necessary to obtain a continuous timing signal for controlling device operation using a synchronous clock extracted from the MFM signal. A problem arises because the clock becomes discontinuous in the synchronization pattern. Also, in cases where the area of the sync pattern is not large enough for all data, the sync pattern portion becomes very short, and the time constants of P, L, and L become small, resulting in incorrect clock phases. The disadvantage is that it becomes vulnerable to defects such as.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide a demodulation circuit that can obtain a proper lock signal from a digitally modulated signal.

〔Example〕

Hereinafter, the present invention will be explained in more detail using the drawings.

FIG. 3 is a block diagram showing the configuration of a modulation section for MFM modulating an input NRZ signal, in which 31 is an AND circuit;
32 is a modulation circuit, and 33 is a synchronization addition circuit. Further, FIG. 4 shows the signal states of each part in the circuit shown in the third diagram.

One of the two input terminals of the AND circuit 31 has the NR to be modulated.
A Z signal (digital signal) a is input, and a gate signal S is input to the other input terminal. As shown in FIG. 4, the gate signal is a pulse signal that is generated in synchronization with the beginning of the NRZ signal a of the flave period T and becomes 0 during a constant (1''W) period.As a result, the output of the AND circuit 31 is As shown in FIG. 4 C, there is a constant 11 W period signal at the tip.

Therefore, of the output d obtained by MFM modulating this signal in the modulation circuit 32, the portion gated by the gate signal is always modulated into an MFM signal having a change point at the boundary of the bit cell. The MFM modulated signal is sent to the synchronization addition circuit 3.
3 is input. In the synchronization addition circuit 33, a gate is applied as described above, and a signal of width W is subjected to MFM modulation according to a predetermined rule. ), a synchronizing signal X is added in which the level signal and the 0 level signal are consecutive 3 bits each.

In this way, the input NRZ signal a is MFM modulated and output together with the synchronization signal X.

FIG. 5 is a block diagram showing the configuration of a demodulator for demodulating the MFM signal output from the modulator shown in FIG. 3, in which 51 is a clock phase determination window detection circuit, 52 is an MFM demodulator, and 53 is P, L, L.

54 is a clock phase determining circuit, 55 is a clock phase inverting circuit, and 56 is a frequency dividing circuit. Further, FIG. 6 shows the signal states of each part in the circuit shown in the fifth diagram.

As mentioned above, the MF to which a synchronization signal is added in the modulation section
The MFM signal is inputted to a phase determination window detection circuit 51. The clock phase determination window circuit 51 uses the synchronization signal and the clock to generate a determination window signal f having a constant width W similar to the gate signal used during modulation. Note that this judgment window signal f has a level inverted from that of the gate signal S described above.

Therefore, this decision window signal f is a 1 times sign corresponding to the section in which the NRZ signal a is gated by the gate signal in the modulation section.

The MFMFM signal is also input to the P Lulu 0 circuit 53.

The Pluru 0 circuit 53 compares a clock with twice the frequency of the demodulated NRZ signal with the input MFMFM signal end, and outputs a clock signal with twice the period of the synchronization clock that should be used for Pluru control. Output. P Lulu 6
The clock signal output from the circuit 53 is frequency-divided by 1/2 by a frequency dividing circuit 56 and inputted to a clock phase inversion circuit 55 as a synchronized clock j. In this way, the synchronized clock outputted from the frequency dividing circuit 56 is
Since it is a clock signal whose frequency is twice as high as 3 and divided into 1/2, it has one of two phases. Incidentally, the P luru 0 circuit 53 always operates in P luru when the MFM signal signal is the same.

The synchronous clock j outputted from the frequency dividing circuit 56 is output as a timing signal to an external device via the clock phase inversion circuit 55 and is applied to the demodulation circuit 52.

Further, the MFM signal signal is also applied to the demodulation circuit 52, and the demodulation circuit 52 demodulates the NRZ signal (digital signal) using this MFM signal synchronization clock j. The thus obtained NRZ signal combination is outputted to an external device and also inputted to the clock phase determination circuit 54.

A determination window signal f from the clock phase determination window detection circuit 51 is inputted to the clock phase determination circuit 54, and when the determination window signal f is a level, it determines whether it is an NRZ signal group or a signal group 1. Here, when the determination window signal f is a level, the NRZ signal g should originally be O. Therefore,
If the NRZ signal is a signal set, the clock phase determination circuit 54 determines that the phase of the synchronous clock signal j used in the demodulation operation in the demodulation circuit 52 is not appropriate, and outputs a phase inversion signal to the clock phase inversion circuit 55. output. on the other hand,
When the determination window signal f is a level, if it is an NRZ signal set, it is determined that the phase of the synchronous clock j is appropriate, and no phase inverted signal is output.

Upon receiving the phase inversion signal, the clock phase inversion circuit 55 converts the synchronous clock j currently input from the frequency division circuit 56.
The phase of the clock is inverted and the phase of the clock is made appropriate.

Therefore, the synchronization clock i applied to the demodulation circuit 52 also has an appropriate phase, and thus the MFM signal can be reliably synchronized.

As described above, according to this embodiment, it is possible to obtain a proper phase synchronization clock for demodulating MFM modulation or data, and therefore, the demodulation operation can be performed honestly. Although VIFM modulation has been described in this embodiment, other modulation methods such as M2FM (Modified
It can be similarly applied to MFM) modulation. In addition, as in the conventional example, P, L, L,
Since P, L, and L are always locked to the MFM signal without being reapplied, the clock never becomes discontinuous.

〔effect〕

As explained above, 2. According to the present invention, it is possible to continuously obtain a synchronized clock with an appropriate phase from a digitally modulated digital signal, and therefore, the demodulation operation can be performed reliably and this synchronized clock can be obtained continuously. The clock can also be effectively used as a timing signal.

[Brief explanation of drawings]

Fig. 1 is a simple explanatory diagram of MFM modulation, Fig. 2 is a timing chart showing conventional demodulation operation, Fig. 3 is a block diagram of an embodiment of the MFM modulation section, and Fig. 4 is each block shown in Fig. 3. FIG. 5 is a block diagram of an embodiment of the MFM demodulation section. FIG. 6 is a diagram showing the output state of each block shown in FIG. 5. 31 is an AND circuit, 32 is a modulation circuit. 33 is a synchronization addition circuit, 51 is a clock phase determination window circuit,
52 is a demodulation circuit, 53 is a 2111 circuit, 54 is a clock phase determination circuit, 55 is a clock phase inversion circuit, and 56 is a frequency division circuit. Applicant: Canon Co., Ltd. Foil Figure 1 (2) Foil Figure 2 ('2) Foil 3 Threshold

Claims (1)

[Claims] In a demodulation circuit that demodulates a digitally modulated digital signal, a clock generation circuit that generates a clock signal synchronized with an input digital signal determines whether the phase of the clock signal generated by the clock generation circuit is suitable. 1. A demodulation circuit comprising: a phase determination circuit for determining the phase of the clock signal; and a clock phase inversion circuit for inverting the phase of the clock signal according to the determination result of the phase determination circuit.