JPS6097445A - Data processor - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a main storage device, etc., by providing a bus signal which indicates that read modify write (RMW) type transfer is in process and providing a processor which performs the RMW type transfer with a means for storing the continuation of the transfer. CONSTITUTION:When the data processor B uses a bus to perform the RMW type transfer, a signal BSBUSY is held at L to secure bus occupation, and signals BSDVLD and BSWRIT are held at L and H respectively to inform the main storage device of a readout request. At this time, the processor B holds the signal BSRMW at L to display the RMW type data transfer. The signals BSWRIT and BSRMW are connected to the same bus, so even a device A detects then and is inhibited from making a bus use request for the RMW type data transfer.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a data transfer method between a data processing device and a main storage device, and particularly relates to a read/modify method.
Concerning a write-type data transfer method.

[Prior art]

Conventionally, read-modify-write (hereinafter referred to as
When performing RMW type data transfer, the bus is occupied until the RMW type data transfer is completed, and the main memory is not used by other data processing devices. A method was used that did not allow data transfer to be performed.

FIG. 1 shows an example of a data processing system, in which data processing devices PI-P transfer data to and from a main memory device MM via a common bus B. In FIG. The BC is a path control device that determines the priority order of bus use requests from data processing devices and grants the right to use the bus to only one device on the path.

FIG. 2 (,) shows the transfer state of the bus when the bus is occupied and RMW type data transfer is performed.

In FIG. 2(a), ■ is a read cycle in which the data processing device reads data from the main memory, processes the read data in a modify cycle ■, and in a write cycle ■, a modify cycle ■ is performed. Writes processed data to main memory.

Conventionally, a data processing device that performs RMW operation is shown in FIG.
), the bus was occupied during the period from (1) to (2), and during this period, other data processing devices could not use the main storage device or the bus.

In other words, in order to stop occupying the bus between ■ and ■ in Figure 2 (,), an attempt is made to release the bus in the read cycle ■ and independently perform the transfer in the write cycle ■. For example, after the read cycle ■, if another data processing device performs an RFi%V operation on the location read in the read L cycle ■, the modify cycle ■
This is because if data is read before the processing performed in , a data mismatch will occur and incorrect processing will be performed. However, in the modify cycle (■) of FIG. 2(a), the data processing device processes the data read and
During this period, the bus is not used, and from the perspective of a data processing device that does not perform RMW operation, this results in a decrease in usage efficiency.

Another method of performing the RMW operation in the prior art is when a bus is provided that transfers data in split cycles. In split cycle bus transfer, RMW type transfer consists of three pass transfers as shown in Figure 2 (b), and between pass transfers, there is a path transfer other than RMW type. If so, the bus and main memory can be used. However, in this case, the main memory is RM
It remembers that the transfer of the W operation was accepted, and rejects the transfer in response to the main storage request notifying that it is an RMW type transfer. On the other hand, the rejected data processing device attempts retransfer until the transfer of the RIVIW operation that was initially accepted by the main storage device is completed. This method uses RM
There is an advantage that path transfer that does not include RMW operation can be performed during the time when path transfer is stalled due to W operation, but a data processing device that makes an RMW operation type request and is rejected will have to retry the path transfer, meaningless path transfer. This had the disadvantage of reducing effective bus traffic.

[Purpose of the invention]

An object of the present invention is to reduce the long bus and main memory occupied by RFi'lW type data transfer by dividing the read cycle and write cycle in RMW type data transfer into two path transfers. It is an object of the present invention to provide a data processing device which can efficiently use a bus and a main storage device without performing RMW type transfer.

(Structure of the Invention) The present invention provides a data processing system in which a main storage device and a plurality of data processing devices transfer data via a common bus, wherein the plurality of data processing devices are connected to a main storage device. R
A means for transmitting a signal to notify other data processing apparatuses that the RMW type data transfer is being performed, including a plurality of data processing apparatuses that perform MW type data transfer, and in the other data processing apparatus, and means for storing that the RMW type transfer continues, whereby the RNI
A data processing device that attempts to transfer data of W d is
The data processing apparatus is characterized in that while the storage means indicates that RMW type data transfer is continuing, a path usage request for performing RMW type data transfer is suppressed.

[Embodiments of the invention]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

3 and 4 are time charts showing the bus interface circuit and operation of a data processing device according to an embodiment of the present invention, and the system configuration is the same as that shown in FIG. 1.

In Figure 4, BSBUSY- is a signal indicating that the path is occupied, and BSREQT- indicates that a device on the bus has issued a path use request to the path controller BC in Figure 1. The signal BSDVLD- indicates that the data is being transferred via the path, and the BSACEP- signal indicates that the device that should receive the data transfer has accepted the data transfer sent in synchronization with the BSDVLD- signal. - This is a signal indicating. The BSDVLD- signal and the BSACEP- signal are combined to perform an asynchronous conversational transfer shown at t2→t3→t4→t5 in FIG. B SWRI T-signal is B
This is a signal sent in synchronization with the SDVLD- signal, and is a signal that notifies the main storage device of whether it is a read request or a write request. The BSRMW- signal is a signal according to the present invention that is sent in synchronization with the 138DVLD- signal, and is a signal that notifies other data processing devices connected to the bus whether or not main memory RMW type data transfer is being performed. be. Here, the IT II or PA+” appended to the end of the signal
When the signal is a logic value II II II (significant value), the sign is given as b II if the signal level is II O II, that is, low level, and 11 + 71 if it is the opposite.

FIG. 3 shows a part of the path interface circuit of the data processing device, and shows only the part related to the present invention, and omits the control circuit for performing interactive transfer, etc.

Here, the operation will be explained with reference to FIGS. 3 and 4. The data processing device will be called A, and the other data processing device that transfers data will be called B.

Time 1 in Figure 4. Assume that data processing device B obtains the right to use the bus and starts RMW type data transfer using the bus. Device B sets the BSBUSY- signal to low level to ensure bus occupancy, and then at time t2 the BSDV
The LD- signal is set to low level and the BSWRIT- signal is set to high level to notify the main memory of a read request. At this time, since device B performs RMW type data transfer,
The signal BSRMW- according to the present invention is set to low level to indicate that RMW type data transfer is being performed. The B5WRI T-signal and BSRMW-signal described above can also be detected in the device A connected to the same path.

In FIG. 3, the BSWRIT- signal is inputted to the NAND dart 10 as the BSWRIT-20 signal through an inverter type bus receiver 3 and an inverter 13.

BSRMW- signal is passed through inverter type path receiver 4 to NAND gate 1 as BSRMW+10 signal.
It is input to 0. The remaining input MYLOCK-00 signal of the NAND gate 10 is the output MYDVL of the flip-flop node (hereinafter simply abbreviated as wa4) 22 which is used to generate the BSDVLD- signal when the device A transfers data.
NAND gate 16 by D+00 and output signal MYRMW+00 of F/F 23 for generating BSRMW- signal when device A performs RMW type data transfer.
Generated by Currently, device A is not performing RMW type data transfer, so the output MYLOCK -00 signal of the NAND gate 16 is not at a high level.
The outputs sMt and ocK-o of the ND dart 10 become low level. As a result, the output 5ETLOCK + OO signal of 9 and AND dart 15 becomes high level, and the D which stores the detection of RMW type data transfer according to the present invention.
- D input of tie f F/F 21 becomes high level.

Upon receiving the read request from device B, the main storage device notifies device B that the transfer has been accepted by setting the BSACEP- signal to a low level. Device B, which has received the BSACEP- signal, sets the BSDVLD- signal to high level.

When detecting that the BSDVLD- signal returns to high level, the main storage device returns the BSACEP- signal to high level. (t2 → t3 → t4 → ts in FIG. 4) In FIG.
21 clock input terminal.

As mentioned above, the D input signal 5ETLOCK +00 of the one type F/F 21 is at high level at this time, so the F/F 21 is set at the leading edge of the BSACEP- signal, and the MMLOCK +00 signal is set at the leading edge of the BSACEP- signal. If the level is not high, the operation shown by the arrow from t3 to t6 in FIG. 4 is performed.

After receiving the read request, the main storage device performs the operation shown in t8→t9→tlO−+tll in FIG. 4 in order to transfer the read data to device B after the access time has elapsed. Device B that received the read data is BS]
3USY- signal returns to high level (t1 in Figure 4)
2) Release the bus.

After this, it becomes necessary for devices N and A to perform bus transfer, and in order to notify the bus control device of a bus use request, the F/F 20 shown in FIG. 3, which generates a device path use request signal, is set. Input 5ETREQ to set F/F 20
The -00 signal is generated by the NAND card, but the input INHRMW of the NAND card is -00
Controlled by signals. The INHRMW -00 signal is the output signal MYRMW+00 of F/F23 and the F/F21
is generated by NAND gate 9 from the output of MMLOCK + 00.

Now, if the type of transfer of the device @A is the hyoro type data transfer, MYRMW+00 is set to high level, and the output MMLOCK+00 of II/F 21 is set to high level as described above. INHRMW because it holds
The -00 signal becomes a low level, and no matter what value the other inputs of the NAND gate 6 have, the bus use request F/F 20 is set unless the MMLOCK + OO signal becomes a low level. No bus use request is generated from device A. However, if the data transfer type of device A is not RMW type transfer, MYR
Since the MW+OO signal is low L/hell, I N
The HRMW-00 signal becomes high level, and device A's bus use request is not blocked by INI-IRIVIW-00, and it is possible to generate a bus use request. In this way, when a device is performing RMW type transfer to the main memory, another device cannot perform RMw type transfer to the main memory. At this time, even if a device other than device B transfers data other than RMW type and the BSACEP- signal is generated on the bus, the BSRMW- signal is at a high level, so the output B of the inverter 14 in FIG.
The SRMW-20 signal is at high level, and a hold circuit consisting of a NAND gate 12, an inverter 8, a NAND dart 7, and an AND gate 15 controls the F/F'21.
holds the state of the output.

Device B, which has finished processing the read data, issues a bus use request (t+3 in Figure 4) in order to write the processed data to the main memory, and if the right to use it is granted, BSBUSY- The signal is set to low level, and as described above (BSDVLD-signal, BSACEP-signal, B
The SMtIT- signal is used to send data to the main memory. This is an RMw type transfer, so I3S
The RMW- signal is set to low level to transfer data.

(t14→t15→t16″LI7″t18 in FIG. 4) To explain this operation in FIG.
The signal is input to the gate 11 as the BSWIζIT+10 signal.

Since it is a 1-write transfer, the BSWRIT + 10 signal is at the no-y level, and I is also a pear-shaped transfer, so the BSRMW
The - signal is at a low level, and the IISRMW+10 signal that turns on the /Z thread/- bar 4 of the inverter type is also at a low level. From this, the output of the NAND gate 11 becomes a low level K, and the output of the AND key 15 becomes a low level, and according to the BSACEP- signal shown at t16 in FIG. The 1llD-type F/F 21 is reset, and the suppression of RMW type transfer requests in the device A is released.

(This operation is explained by the arrow from t16 to t7 in FIG. 4.) Finally, the case where a plurality of data processing devices simultaneously issue RMw type data transfer requests will be described.

The Q output signal MYRMW-00 signal of the RMW type transfer request F/F 23 is connected to the D input of the bus use request F/F 20, and the inverted output of the path occupancy display signal BSBUSY- signal is connected to the clock input. are connected via an inverter type bus receiver 17. Currently, in devices that make RMW type data transfer requests, MYRIlm-0
Since the 0 signal is at a low level, the bus use request F/F 20 is reset at the leading edge of the BSBUSY- signal, and the F/F 20 is reset.
To reset F20, the output 5ETREQ-00 signal of NAND dart 6 must go low. If there is a device that makes an RMW type data transfer request on the bus and obtains the right to use the bus, as mentioned above, the F/F 21 (D output MMLOCK + OO signal becomes 7% error level, If the bus use request includes RMW type transfer, the output INHRMW of NAND gate 9
The -00 signal goes low to prevent the F/F 20 from being reset. This allows multiple devices to be RM
Even if a bus use request including W-type transfer is generated, RF#-type transfer will not intervene again between t12 and t14 in FIG. 4.

〔Effect of the invention〕

As explained above, the present invention provides a bus signal indicating that RMW type transfer is being executed and means for storing in a data processing device that performs RMW type transfer that RMW type transfer is being continued. By providing this, the read cycle and write cycle of the ribbed type transfer are divided into two and transferred. In particular, it has the effect of improving the usage efficiency of the main storage device and the bus.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of seven data processing systems that share the main memory, and Figure 2 is a block diagram showing an example of seven data processing systems that share the main memory.
Figure 3 is a diagram showing the operation of the light, Figure 3 is a diagram showing an embodiment of the present invention, and Figure 4 is a diagram showing the operation of the embodiment of the present invention.
It is a chart. In the figure, BC...bus control device, MM...main storage device, P1-Po...data processing device, BSBUSY-.
...Bus occupancy signal, BSREQT-...Bus use request signal, BSDVLD-...Bus data transfer signal, BSA
CEP-...Bus data transfer/receipt is received signal, BSWR
I T-...Main memory write signal, BSRMW
-...-RMW type transfer display signal, MMLOCK + 范 1 fig.

Claims (1)

[Claims] 1. In a data processing/system in which a main storage device and a plurality of data processing devices transfer data via a common bus, the plurality of data processing devices
Multiple r- for modify write type data transfer
The data processing device that performs the read-modify-write type data transfer, including the read-modify-write type data transfer, informs other data processing devices that it is executing the data transfer associated with the read-modify-write type data transfer. It has a means for sending a notification signal and a means for memorizing that the read-modify-write operation is continuing in another data processing device. The data processing device attempting to transfer data performs a read-modify-write operation on the main memory while the storage means indicates that the read-modify-write operation is continuing. A data processing device characterized by suppressing bus usage requests for other purposes.