JPH04155549A - Address competition preventing system - Google Patents

Abstract

PURPOSE:To offer a system which can be easily realized and whose operation is certain by first inhibiting a write-in operation, and then reading readout data by a readout address, at the time of reading the data of a dual port RAM. CONSTITUTION:There is a case that the write-in operation and readout operation of data are asynchronous in a dual port RAM 1. When the flag of readout start(the flag of write-in inhibition) of the output of a read-in flag part 4 is turned ON during writing-in, a data write-in controlling part 3 doesn't immediately inhibit the write-in operation, and makes the readout starting flag of the output of the read-in flag part 4 effective(write-in inhibition) at the time of the completion of the write-in operation. Thus, the write-in operation is necessarily stopped at the time of the readout of the data in the dual port ROM 1, so that there is not any possibility of an address competition, the constitution can be simple, and the operation can be certain.

Description

[Detailed description of the invention] 〔overview〕 In a circuit using dual port RAM.

Concerning a method for preventing address conflict collisions, we aim to provide a method for preventing address conflict in dual port RAM that is easy to implement and reliable in operation.
A data collection unit that specifies the address of write data to be input to M and collects and outputs the corresponding write data, and a data collection unit that receives a data collection completion notification from the data collection unit and outputs data at the write address of the data collection unit. a data write control unit that generates a write speed control signal that controls writing of data and a write stop signal that stops writing write data; and an on/off control unit that instructs the data write control unit to stop writing and start reading. Data is written from the chip select terminal and the CS picture signal that specifies the write area to the chip select terminal of the dual port RAM using the read flag unit that sends an off signal and the write side picture signal from the data write control unit. A CS control unit that generates a CS control signal that causes the control unit to stop writing to a designated write area and start reading based on the ON signal of the output of the read flag unit;
3 control signal, the writing of write data to the dual port RAM using the write address is stopped, and then the read data is read using the read address.

[Industrial application field]

The present invention provides an address conflict prevention system dual port RAM that prevents address conflicts in a dual port RAM circuit having two ports for writing and reading data.
is used in any combination of software-to-software, software-to-hardware, hardware, or hardware-to-hardware, but in that case, an address conflict prevention method is required to ensure that write addresses and read addresses do not collide. required. There are various methods for preventing address conflicts, but in any case, it is required that the structure is simple and the operation is reliable.

[Conventional technology]

A in FIG. 6 is an example of a conventional address conflict prevention method in which a dual port RAM is used for software-to-software.
422, the MC 6802 of the writing side CPU writes data, and the MB 6802 of the reading side CPtJ reads it. In this case, the dual-port 4RAM's own conflict detection function ``busy signal J BLISY'' was used to stop the operation of one CPU during the conflict time, thereby solving the problem of data loss occurring during conflict. 6B is an example similarly used for software-to-software, in which the order of access to the dual port RAM is established between the CPUs on both sides.
That is, a protocol that defines an access sequence is provided, and writing and reading operations are performed at completely different timings to prevent conflicts.

[Invention or problem to be solved]

However, in the conventional method shown in Fig. 6, one CPLI
Since the operation of the CPU is stopped, there are problems such as, for example, an emergency interrupt request to the CPU cannot be accepted, and it is difficult to check the operation of the program when the program is stopped.

In addition, the conventional method shown in FIG. 6B establishes an access sequence, so that write and read operations are performed reliably, but it is complicated because detailed protocols such as sequential execution arrangements must be established. The problem with the use of hardware versus software is that sequential execution methods are difficult to implement. An object of the present invention is to provide an address conflict prevention method in a dual port RAM that is easy to implement and reliable in operation.

[Means to solve the problem]

This issue is based on the basic concept of giving priority to the data read operation in a dual port RAM and always stopping the write operation before starting the read operation. A data collection unit 2 specifies the address of write data input to port RAM 1, collects and outputs the corresponding write data, and receives a data collection completion notification from the data collection unit and outputs the output of the data collection unit. A data write control unit 3 that generates a write control timing signal that controls writing of write data from a write address and a write stop timing signal that stops writing of write data, and The chip select terminal C of the dual port RAMI is controlled by the read flag section 4 which sends an on/off signal to command the stop of reading and the start of reading, and the write control timing signal from the data write control section.
A CS control signal that specifies the write area to S and an ON signal of the output of the read flag unit 4 from the chip select terminal CS to the data write control unit 3 stop writing to the specified write area and start reading. CS control signal to start and C to generate
and an S control section 5, the CS control section 5
Dual port RAM
This is achieved by the present invention, which is configured such that writing of write data using a write address to No. 1 is stopped, and then read data is read using a read address.

[Effect]

The present invention provides the dual port RAMI shown in FIG.
Since the data write operation and the data read operation may be asynchronous, if the read start flag (write inhibit flag) output from the read flag section 4 is turned on during writing,
The data write control section 3 does not immediately inhibit the write operation, but waits for the end of the write operation before the read start flag output from the read flag section 4 becomes valid (write prohibited). Therefore, in the dual port RAMI, when data is read, the write operation is always stopped, so there is no chance of address conflict.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the address conflict prevention method according to the embodiment of the present invention, and is an example in which the write side of a dual port RAM operates periodically by hardware, and the read side operates at random timing by software. It is. 1 to 5 in FIG. 2 have the same functions as the same numbers in FIG. In FIG. 2, the data collection section 2 is a 4-byte input latch circuit, and is capable of so-called 3-state output. The data write control unit 3 includes a frequency division counter 3a, an SR flip-flop 3b, a quaternary counter 3c, a decoder 3d, and a write clock generation circuit 3.
The frequency division counter 3a can simply count the basic clock and output a carry periodically. The quaternary counter 3C is a binary counter with an enable function, and here, a quaternary counter is shown as an example.

The write clock generation circuit 3e enables the output of the SR flip-flop 3b and allows the clock to pass for only the corresponding period, and is like an AND gate. The CS control section 5 is a JK flip-flop 5.
JK flip-flop 5a has a basic gate on the input side. Read flag section 4
is composed of a register that temporarily holds a flag, and synchronizes the read start on/off signal outputted from the register with the hardware side, and the NAND gate 5b controls write inhibition to the dual port RAM l. It is a gate to do. In normal operation, the SR flip-flop 3 is
When b is set, the quaternary counter 3C, which has been in a disabled state, is enabled, and the write control signal B is made to be in a write enabled state.

Every time the quaternary counter 3C updates the counter value, the decoder 3d operates, and the input Ao of the dual port RAMI,
Only 1 byte of data specified by the separate data designation address K of A+ is output from the collected data latch circuit 2, and at the same time, the desired data is written to the corresponding memory address by the write enable signal WE generated by the write clock generation circuit 3e. .

Inputs A2 to A of the dual port RAMI. The separated data designation address E is fixed during this write operation, and changes only when separated data of a different address is collected, and the time of change is the data write notification signal of the frequency division counter 3a. It is designed to be carried out during the occurrence cycle of . Therefore, the periodic generation of the data write notification signal,
Since the collected data has been determined before this signal is generated, the dual port RAMI can perform a 4-byte write operation or cycle for one address, as shown in the memory configuration diagram in Figure 4. It is carried out according to FIG. 3 is a normal operation flowchart of the embodiment of FIG. 2. On the other hand, in contrast to the above-mentioned periodic writing by hardware, software accesses the dual port RAM at random timing (
(read), the operation is as follows. FIG. 5 is a flow diagram at the time of reading.

First, before accessing (reading) the software or dual port RAM 1, set the read start flag to register 4 “1”.
".This sets the read signal I or °'0".
(OFF) to "1" (ON), and the output Q of the JK flip-flop 5a changes from 1" to '0". In this case, the J input performs AND processing of the read signal I and the inversion of the write control signal B, and in the case of ■ in the read flow diagram of FIG.
Therefore, the J input of the JK) 1 block flop 5a becomes "do", the K input becomes "0", the Q output becomes "0", and the CS signal to the dual port RAM 1 becomes "I".
Fixed. In the case of σ■ in Figure 5, the heart is being written, so be sure not to fix it to C3 (P or 1) immediately.
After waiting 4 hours for the end of writing, the CS signal is set to "1", indicating that writing is forcibly prohibited. In addition, the JK flip-flop 5acDQ output (write stop signal J) is
In order to prohibit enabling of the external data generation side and stop the counting operation of the frequency division counter 3a, F is shown in the flow diagram.
A suspension period J occurs. In other words, during the software read period, hardware operations are stopped and write operations are also prohibited, so that the dual port RAM 1 is not given any opportunity for address conflict during the read period.

If data is sent from the outside during the reading period, the data will be written incorrectly, so data generation on the outside side is also stopped. Yo=
So, as long as the software read time, the next write operation will be I
delay.

〔Effect of the invention〕

As explained above, according to the present invention, when data is read from the dual port RAM, the write operation is first inhibited, thereby completely eliminating the chance of contention, and even if the write operation is stopped, It is possible to obtain the effect of being able to avoid writing errors in the collected data.

[Brief explanation of drawings]

Figure 1 is a principle diagram showing the basic configuration of the address conflict prevention method of the present invention, Figure 2 is a block diagram showing the configuration of an embodiment of the invention, and Figure 3 is for explaining the operation of the embodiment of the invention. 4 is a flowchart of the normal operation of the dual port RA used in the embodiment of the present invention.
FIG. 5 is an operation flow diagram at the time of reading to explain the operation of the embodiment of the present invention. FIG. 6 is a block diagram and protocol diagram of a conventional dual-port RAM address conflict prevention method. be. In the figure, ■ is a dual port RAM, 2 is a data collection section, 3 is a data write control section, 4 is a read flag section,
5 is a CS control section.

Claims (1)

[Claims] Dual port RAM with 2 ports for writing and reading
In this circuit, the dual port RAM (1
); a data collection unit (2) that specifies the address of the write data to be input into the data collection unit and collects and outputs the corresponding write data; and a data collection unit (2) that receives a data collection completion notification from the data collection unit and writes the output of the data collection unit. A data write control section 3 generates a write control signal for controlling writing of data at an address and a write stop signal for stopping writing of write data, and a data write control section 3 for generating a write control signal for controlling writing of data at an address and a write stop signal for stopping writing of write data, and for controlling writing stop and start of reading to the data write control section. A read flag section 4 sends out an on/off signal to command, and a CS control signal that specifies a write area to a chip select terminal (CS) of the dual port RAM 1 by a write control signal from the data write control section. , a CS control unit that generates a CS control signal from the chip select terminal to the data write control unit (3) to stop writing to a designated write area and start reading based on the ON signal of the output of the read flag unit 4; (5) The CS control signal output from the CS control unit is used to stop writing the write data to the dual port RAM using the write address, and then read the read data using the read address. Featured address conflict prevention method.