JPS6095662A - Memory error correcting method - Google Patents

Abstract

PURPOSE:To prevent fundamentally generation of a memory error by constituting a memory so that a memory address of a memory area in which an error is detected does not execute access. CONSTITUTION:When a memory detecting circuit 2 sends out error detecting information to a register circuit 4, the register circuit 4 stores and holds received memory address information. In this state, when memory address information of a memory area in which an error is detected is sent out again from said circuit, a comparing circuit 5 compares this memory address information with the memory address information held in the register circuit 4, and sends out a coincidence signal to a multiplexer circuit 7. The multiplexer circuit 7 switches that which has received the memory address information from said circuit before that time, to a register circuit 6 side, fetches the memory address information from the register circuit 6, and executes access to the fetched memory area concerned, so that a memory address of a memory area in which a detected error does not execute access.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a memory error correction method for correcting memory errors by isolating an error-occurring area of memory.

(b) Background of the Technology As the use of information processing devices becomes more sophisticated and complex, more stringent requirements are placed on the reliability of the information handled. Furthermore, in the unlikely event that an error occurs, it has become necessary to implement countermeasures using various error recovery methods.

In particular, regarding memory errors that store information, it is required to improve the quality of the memory itself and to handle memory errors reliably.

(C) Prior Art and Problems A conventional method for correcting memory errors will be described with reference to one drawing.

FIG. 1 shows a conventional memory error correction method.

In the figure, 1 is a memory, and 2 is a memory detection circuit.

3 indicates an error correction circuit (hereinafter referred to as an ECC circuit).

Conventionally, data was read from memory 1 and EC was performed one byte at a time.
It is applied to the C circuit 3 (which usually consists of a 1-byte shift register and has the ability to automatically correct a 1-bit error). Here too.

When memory detection circuit 2 detects a 1-pin error, F
The CC circuit 3 automatically corrects the signal and sends it to the next circuit (not shown).

However, although the ECC circuit 3 corrects errors in the read data, it does not perform any operations on the area where the error has occurred, so there is always an internal error factor. If another bit error occurs in the area where the cause is present, it becomes a 2-bit error and cannot be corrected by the ECC circuit 3.

(d) Purpose of the Invention The object of the present invention is to provide a novel memory error correction method that eliminates the above-mentioned drawbacks, and in particular, by separating the memory area where the memory error has occurred and allocating it to two alternative memory areas. The object of the present invention is to realize a memory error correction method that fundamentally eliminates the occurrence of memory errors.

(e) Structure of the Invention The present invention provides a device comprising a large-capacity memory for storing information and a memory error detection circuit for detecting errors in the memory, in which a memory error is detected by the memory error detection circuit. This can be achieved by a memory error correction method characterized in that the cause of the memory error is fundamentally removed by allocating the separated memory area to a memory area for use as an alternative memory area.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of the memory error correction method according to the present invention.

In the figure, 4 and 6 are register circuits, 5 is a comparator circuit,
7 each indicate a multiplexer circuit.

In this embodiment, a memory 1. 2. A memory detection circuit that detects whether there is an error in the data read from the memory 1. An ECC circuit that has the ability to automatically correct a 1-bit error in one memory area 3. A register circuit 4 that stores and holds the memory address of the memory area detected by the memory detection circuit 2. An alternative comparator circuit 51 that compares the memory address information sent from the previous circuit (not shown) with the memory address information held in the register circuit 4 and outputs a match signal to the multiplexer circuit 7 if they match. 6. A register circuit that stores the memory address of the memory for use. A multiplexer circuit 7 that accesses the memory address of the alternative memory stored in the register circuit 6 based on the match signal from the comparator circuit 5.
It is composed of

Next, the operation of this embodiment will be explained.

The multiplexer circuit 7 receives the memory address of the memory 1 to be read from the previous circuit (not shown), accesses the corresponding memory address, and sends the read data to the next circuit (not shown) via the ECC circuit 3. be done. here,
When there is a 1-bit error in the read data and the error is detected by the memory detection circuit 2, the ECC circuit 3
The error correction function of the CC circuit 3 automatically corrects the error and sends the data to the next circuit (not shown).

On the other hand, when the memory detection circuit 2 sends error detection information to the register circuit 4, the register circuit 4 stores and holds the received corresponding memory address information. At this point, the normal data in the memory area where the error was detected by a circuit (not shown) is rewritten to an alternative memory area, and the memory address information of the alternative memory area is stored in the register circuit 6. It is assumed that there is

When the memory address information of the memory area in which the error was detected is sent again from the previous circuit (not shown) in the above state, the comparator circuit 5 retains this memory address information and the register circuit 4. If they match, a match signal is sent to the multiplexer circuit 7. The multiplexer circuit 7 switches the memory address information from the previous circuit (not shown) to the register circuit 6 side and extracts the memory address information of the corresponding alternative memory area from the register circuit 6. The extracted memory area is accessed, and the memory address of the memory area where the error was detected is not accessed.

Note that the number of alternative memory areas is set depending on the situation of the device in which the memory 1 is used.

(g) Effects of the Invention According to the present invention as described above, the memory address of a memory area where an error has been detected is not accessed, and the occurrence of memory errors can be fundamentally prevented.

[Brief explanation of the drawing]

FIG. 1 shows a conventional memory error correction method, and FIG. 2 shows an embodiment of the memory error correction method according to the present invention. In the figure, 1 is a memory, and 2 is a memory detection circuit. 3 is an ECC circuit, 4 and 6 are register circuits, 5 is a comparator circuit, and 7 is a multiplexer circuit. a i Figure Z (2)

Claims (1)

[Claims] In a device comprising a large-capacity memory for storing information and a memory error detection circuit for detecting errors in the memory, a memory area in which a memory error is detected by the memory error detection circuit is separated and set as an alternative memory area. A memory error correction method characterized by allocating the separated memory area.