JPS6094768A - Photosemiconductor device - Google Patents
Photosemiconductor deviceInfo
- Publication number
- JPS6094768A JPS6094768A JP58202208A JP20220883A JPS6094768A JP S6094768 A JPS6094768 A JP S6094768A JP 58202208 A JP58202208 A JP 58202208A JP 20220883 A JP20220883 A JP 20220883A JP S6094768 A JPS6094768 A JP S6094768A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light
- emitter layer
- resistance
- receiving part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 3
- 230000007423 decrease Effects 0.000 abstract description 5
- 230000000630 rising effect Effects 0.000 abstract description 3
- 206010034960 Photophobia Diseases 0.000 abstract description 2
- 208000013469 light sensitivity Diseases 0.000 abstract description 2
- 230000035945 sensitivity Effects 0.000 abstract description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 10
- 230000036211 photosensitivity Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 239000013307 optical fiber Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/111—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors
- H01L31/1113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors the device being a photothyristor
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、エミッタ短絡型の光半導体装置に係シ、特に
光半導体装置の光感度を向上させる構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an emitter short-circuit type optical semiconductor device, and particularly to a structure for improving the photosensitivity of the optical semiconductor device.
第１図は、エミッタ短絡型の光半導体装置のひとつであ
る従来の光サイリスタの断面構造を示している。図にお
いて、半導体基体１は積層状になっておシ、例えば、１
３はｎ型導電性の第１エミッタ層であシ、その上に順次
ｎ型導電性の第１ペース層１２．ｎ型導電性の第２ベー
ス層１１．ｎ型導電性の第２エミッタ層１ｏが積層状に
形成され、各層間にｐｎ接合ＪＩ−Ｊｓができている。FIG. 1 shows the cross-sectional structure of a conventional optical thyristor, which is one of the emitter short-circuit type optical semiconductor devices. In the figure, a semiconductor substrate 1 is arranged in a layered manner, for example, 1
3 is a first emitter layer of n-type conductivity, and a first paste layer 12 of n-type conductivity is sequentially formed thereon. N-type conductive second base layer 11. A second emitter layer 1o of n-type conductivity is formed in a laminated manner, and a pn junction JI-Js is formed between each layer.
第１エミッタ層１３の裏面にはアノード電極２１が低抵
抗接触している。一方、表面側では、第２エミッタ層１
０と第２ペース層１１とが露出１〜、その上にカソード
電極２００が低抵抗接触している。従って、ｐｎ接合Ｊ
３は短絡されている。更に、第２ベース層１１内には、
第２エミッタ層１０から離れ、表面に露出する第２エミ
ッタ層１０と同じ導電型の受光エミツタ層１０ａが形成
され、この受光部エミツタ層１０ａと第２ベース層１１
との間のｐｎ接合Ｊ４の露出部が受光部電極２０１で短
絡されている。An anode electrode 21 is in low resistance contact with the back surface of the first emitter layer 13 . On the other hand, on the surface side, the second emitter layer 1
0 and the second paste layer 11 are exposed 1~, and the cathode electrode 200 is in low resistance contact thereon. Therefore, pn junction J
3 is shorted. Furthermore, in the second base layer 11,
A light-receiving emitter layer 10a of the same conductivity type as the second emitter layer 10 is formed apart from the second emitter layer 10 and exposed to the surface, and this light-receiving emitter layer 10a and the second base layer 11
The exposed part of the pn junction J4 between the two is short-circuited by the light-receiving part electrode 201.
この光サイリスタは、例えば光ファイバ３０からの光３
１でまず点弧する受光部サアリスタとしての第１の４層
領域Ｔｌ１ｌ とこの受光部サイリスタの電流で点弧す
る主サイリスタとしての第２の４層領域Ｔｈ２とからな
る。第１の４層領域と第２の４層領域の間に補助サイリ
スタとしての第３の４層領域を形成し、第１の４層領域
で発生する電流を増幅して主サイリスタに供給すること
も可能である。This optical thyristor, for example, receives light 3 from an optical fiber 30.
It consists of a first four-layer region Tl1l as a light-receiving thyristor that is first fired at 1, and a second four-layer region Th2 as a main thyristor that is fired by the current of this light-receiving thyristor. A third four-layer region as an auxiliary thyristor is formed between the first four-layer region and the second four-layer region, and the current generated in the first four-layer region is amplified and supplied to the main thyristor. is also possible.
とのような構造を採るのは、大電流を制御する場合、初
期点弧領域である光照射領域に大電流が集中することを
防ぎ、小電流のうちに導通面積を補助サイリスタ、更に
主サイリスタへと広げ、ジ２ ニール熱による素子破壊
を防ぐためである３、こうすると、主サイリスタよシも
補助サイリスタ、それよりも受光部サイリスタの点弧感
度を高くてき＼受光部サイリスタの高感度化を図ること
ができる。The reason for adopting this structure is that when controlling a large current, it prevents the large current from concentrating on the light irradiation area, which is the initial ignition area, and reduces the conduction area during the small current to the auxiliary thyristor and then the main thyristor. This is to prevent element destruction due to Neil heat.3 By doing this, the firing sensitivity of the main thyristor, the auxiliary thyristor, and even the light-receiving thyristor can be increased. can be achieved.
光による点弧現象に関する発明者等の研究の結果、第１
図の受光部エミッタ層１０ａｆｃ通して光が照射される
受光部サイリスタをもつ光サイリスタでは、光によって
第１エミツタ層１３．第１ベース層１２．第２ベース層
１１に発生し主サイリスタのカソード電極２００へ流れ
るｉ！流ｉＩ、のほかに、受光部サイリスクの第２ベー
ス層１１と受光部エミツタ層１０ａのｐｎ接合Ｊ４によ
る太陽電池効果で受光部電極２０１を通って流れる電流
１ｐがあることが発見された。これらの電流の和ｉ ｂ
十ｉｐと第２ベース層１１の横方向の抵抗Ｒｍとによ
り、光照射領域下の受光部エミツタ層ｉｏａと第２ベー
ス層１１とのＪ４接合に１１＃１方向ノ’Ｉ［圧（Ｉ
ｂ ＋ ｔ ｐ ） Ｘ Ｒｎが加わる。この電圧がＪ
４接合のしきい値電圧よシ大きくＡると、受光部エミツ
タ層１０ａから多量の電子が注入されることから、アノ
ード・カソード電極間に印加された電圧を阻止していた
Ｊ２接合の空乏層が第１の４層領域において消滅し、受
光部サイリスタは点弧する。この受光部サイリスタが点
弧するときの最小の光照射量を最小点弧光入力ＰＧＴと
呼ぶことにする。As a result of the inventors' research on the ignition phenomenon caused by light, the first
In the optical thyristor having a light receiving part thyristor in which light is irradiated through the light receiving part emitter layer 10afc shown in the figure, the first emitter layer 13. First base layer 12. i! generated in the second base layer 11 and flowing to the cathode electrode 200 of the main thyristor! It has been discovered that in addition to the current iI, there is a current 1p flowing through the light receiving electrode 201 due to the solar cell effect due to the pn junction J4 between the second base layer 11 of the light receiving part silice and the light receiving part emitter layer 10a. The sum of these currents i b
Due to the resistance Rm in the lateral direction of the second base layer 11 and the resistance Rm in the lateral direction of the second base layer 11, a pressure (I
b + t p ) X Rn is added. This voltage is J
If A is larger than the threshold voltage of the J2 junction, a large amount of electrons will be injected from the emitter layer 10a of the light receiving part, so the depletion layer of the J2 junction that was blocking the voltage applied between the anode and cathode electrodes will disappears in the first four-layer region, and the light receiving thyristor fires. The minimum amount of light irradiation when the light receiving thyristor is fired will be referred to as the minimum firing light input PGT.
最小点弧光入力ＰＧＴは、第１図のような構造で４ｋＶ
程度の阻止電圧をもつ光サイリスタでは、５ｍＷ程度で
あシ、ターンオン時間を短くするには、更にＰＧＴの５
倍以上の光量が必要である。しかし、現状では、発光素
子と光ファイバの光結合効率が数チと低いため、光ファ
イバからの光出力は小さく、そのような大きな光量を、
発光素子によシ安定的に供給するのは困難で、Ｐ（ＩＴ
を小さくすることが望ましい。最小点弧光入力Ｐｏｔを
小さくするには、抵抗ＲＢを大きくし、小さな１ｂ−４
−ｔｐの電流でＪｎ４接合がしきい値電圧に達するよう
にすればよい。The minimum ignition light input PGT is 4kV with the structure shown in Figure 1.
For an optical thyristor with a blocking voltage of about 5 mW, it is about 5 mW, and to shorten the turn-on time, it is necessary to further reduce the PGT's 5 mW.
More than double the amount of light is required. However, at present, the optical coupling efficiency between the light emitting element and the optical fiber is low, on the order of several orders of magnitude, so the optical output from the optical fiber is small, and such a large amount of light cannot be transmitted.
It is difficult to stably supply light to the light emitting element, and P(IT
It is desirable to make it small. To reduce the minimum ignition light input Pot, increase the resistance RB and use a small 1b-4
The Jn4 junction may reach the threshold voltage with a current of -tp.
ここで、第１図に示すような光サイリスタのアノード電
極２１に正、カソード電極２００に負の急峻な立ち上シ
の電圧を加えると、ｔＴ２接合にｉｂと同じような変位
電流が流れる。この変位電流と抵抗Ｒｍとにより、第２
ベース層１１と第２エミッタ層１０との間の５３接合及
び第２ペース層と受光部エミツタ層１０との間のＪ４接
合が順バイアスされ、光照射しなくても、光サイリスタ
が誤点弧してしまう。誤点弧しない電圧上昇率の限界値
をｄ ｖ ／ ｄ を耐１．という。先に述べた抵抗′
ｆＬＩＩを大きくすることは、ｄｖ／ｄｉ耐計を低下さ
せるので好ましくない。Here, when a positive, steeply rising voltage is applied to the anode electrode 21 of the optical thyristor as shown in FIG. 1 and a negative voltage is applied to the cathode electrode 200, a displacement current similar to ib flows through the tT2 junction. This displacement current and resistance Rm cause the second
The 53 junction between the base layer 11 and the second emitter layer 10 and the J4 junction between the second paste layer and the light-receiving emitter layer 10 are forward biased, and the optical thyristor is erroneously fired even without light irradiation. Resulting in. The limit value of the voltage rise rate that does not cause false ignition is d v / d 1. That's what it means. The resistance mentioned earlier
Increasing fLII is not preferable because it lowers the dv/di resistance.
以上の事柄をまとめると、最小点弧光入力ＰＧ？を小さ
くするために抵抗Ｒ１を大きくした場合に、ｄ ｖ ／
ｄ を耐量が逆に低下してしまう欠点があった。To summarize the above matters, the minimum ignition light input PG? When resistor R1 is increased to reduce d v /
There was a drawback that the withstand capacity of d was conversely reduced.
本発明の目的は、ｄｖ／ｄｔｉｌｌＩｔｔの低下を来さ
ずに、光入力に対して高感度の光半導体装置を提供する
ことである。An object of the present invention is to provide an optical semiconductor device that is highly sensitive to optical input without causing a decrease in dv/dtillItt.
本発明は、太陽電池効果により発生する起電力を効率よ
く引き出すために第２ベース層１１と受光部エミツタ層
１０ａとの間に抵抗分を介在させて光感度を高める一方
、ｄ ｖ ／ ｄ を耐量に対しては、この抵抗分が影
響を及ぼさないようにして、最小点弧光入力ＰＯＴとｄ
ｖ／ｄｔ耐量を独立に設定できるようにしたものである
。In the present invention, in order to efficiently draw out the electromotive force generated by the solar cell effect, a resistance component is interposed between the second base layer 11 and the light-receiving part emitter layer 10a to increase the photosensitivity, while at the same time increasing the d v / d. In order to prevent this resistance from affecting the withstand capacity, the minimum ignition light input POT and d
This allows the v/dt tolerance to be set independently.
以下、本発明の実施例を第２図〜第６図により説明する
。Embodiments of the present invention will be described below with reference to FIGS. 2 to 6.
第２図は、本発明の光半導体装置のひとつの実施例を示
しており、第１図の従来例と同一符号を付した部分は同
一機能を果す。この第１実施例の特徴は、第１の４層領
域のｐ型溝電性の第２ベース層１１とｎ型導電性の受光
部エミツタ層１０ａとの間に外付は抵抗Ｒを介在させて
いる点にある。FIG. 2 shows one embodiment of the optical semiconductor device of the present invention, and parts given the same reference numerals as those in the conventional example of FIG. 1 perform the same functions. The feature of this first embodiment is that an external resistor R is interposed between the second base layer 11 with p-type groove conductivity and the light-receiving part emitter layer 10a with n-type conductivity in the first four-layer region. The point is that
従って、従来例の受光部電極２０１ば、この実施例では
、第１の電極２０２と第２の電極２０３とに分割されて
いる。Therefore, the light-receiving section electrode 201 of the conventional example is divided into a first electrode 202 and a second electrode 203 in this embodiment.
抵抗層を介在させたことにより、第２ベース層１１と受
光部エミツタ層１０ａとの間に順方向の電圧降下を生じ
させる成分として、（１ｂ−１−１ｐ ）ｘｎ、ｎのほ
かに、ｔ、ＸＲが加わるために、Ｊ４接合をしきい値電
圧に高め易く、光感度が向上する。By interposing the resistance layer, in addition to (1b-1-1p)xn, n, t , XR are added, it is easy to raise the J4 junction to the threshold voltage, and the photosensitivity is improved.
抵抗Ｒを付加したことのｄｖ／ｄｔ耐−畦に与える影響
を考慮してみると、アノード電極２１とカソード電極２
００間に負の急峻な立ち上りの電圧を加えた場合は、電
流Ｉ、の影響はなく、ｉｂのような電流のみが流れるた
めに、第２ベース層１１と受光部エミツタ層１０ａとの
間に順方向の電圧降下を生じさせる抵抗分としては、Ｔ
Ｌ＊のみが関与する。従って、抵抗Ｒを介在させること
によ、９、ｄｖ／ｄｔ耐量が低下することは危い。Considering the effect of adding the resistance R on the dv/dt resistance, the anode electrode 21 and the cathode electrode 2
When a steep negative rising voltage is applied between 00 and 00, there is no effect of current I and only current ib flows, so that there is a gap between second base layer 11 and light receiving emitter layer 10a. The resistance component that causes the voltage drop in the forward direction is T
Only L* is involved. Therefore, by interposing the resistor R, there is a danger that the 9.dv/dt tolerance will be reduced.
第３図は、抵抗Ｒを変えたときの最小点弧光入力ＰＯＴ
の変化を示す図である。Ａ点から抵抗層を大きくするに
つれてＰ（ＩＴが低下し、すなわち光感度が向上する。Figure 3 shows the minimum ignition light input POT when changing the resistance R.
FIG. As the resistance layer becomes larger from point A, P(IT decreases, that is, the photosensitivity improves.
更に抵抗Ｒを大きくすると、最小点弧光入力はＢ点で極
小値に達し、その後は急速に光感度が悪化する。との光
感度の低下は、光サイリスタの点弧直前から始まる受光
部エミツタ層１０ａから第２ベース層１１への電子注入
により、受光部エミッタ層１０ａ、抵抗Ｒ９第１の電極
へと流れる電流が生じ、この電流が抵抗Ｒを電流量、と
は逆方向に流れるため、第２ベース層１１と第２エミッ
タ層１０との間に逆方向の電圧降下を生じることと、抵
抗Ｒにより電子注入の電流が抑制されることに起因する
。When the resistance R is further increased, the minimum ignition light input reaches a minimum value at point B, and thereafter the light sensitivity rapidly deteriorates. This decrease in photosensitivity is due to the injection of electrons from the light receiving part emitter layer 10a to the second base layer 11 starting just before the ignition of the optical thyristor, and the current flowing to the light receiving part emitter layer 10a and the first electrode of the resistor R9. Since this current flows through the resistor R in the opposite direction to the current amount, a voltage drop occurs in the opposite direction between the second base layer 11 and the second emitter layer 10, and the resistor R causes an increase in electron injection. This is due to the current being suppressed.
次に抵抗層の好ましい値について述べる。第４図は、受
光部サイリスクの第２ベース層１１と受光部エミツタ層
１０ａとの間の太陽電池効果によって生ずるこれら層間
の電圧Ｖ１ｍと電流ｉ、の関係を示す図である。発明者
らの研究の結果、第３図のＡ、Ｂ、Ｃ各点に対応する抵
抗値を重ねて表示してみると、Ｐｏｔが極小値を示すＢ
点の抵抗は、第４図において、太陽電池の起電力（ｉ、
ＸＶｎＰ＋）を最も効率よく引き出す抵抗であることが
わかった。つまシ、第２ベース層１１の横方向の抵抗Ｒ
＋＋と抵抗Ｒとの和を、太陽電池の起電力を効率よく引
き出す値に調整することで、光感度を最大にできること
が発見された。なお、Ａ点ではＶＢ ｚ０Ｓ
が小さく、第２べ・−ス層１１と受光部エミツタ層１０
との間に順方向の電圧降下を生じさせる効果が少ない。Next, preferred values for the resistance layer will be described. FIG. 4 is a diagram showing the relationship between the voltage V1m and the current i between the second base layer 11 of the light-receiving part and the emitter layer 10a of the light-receiving part caused by the solar cell effect between these layers. As a result of the inventors' research, when the resistance values corresponding to points A, B, and C in Fig. 3 are superimposed and displayed, Pot shows the minimum value at B.
The resistance at a point is the electromotive force (i,
It was found that this is the resistor that brings out the most efficient XVnP+). Lateral resistance R of the second base layer 11
It has been discovered that photosensitivity can be maximized by adjusting the sum of ++ and resistance R to a value that efficiently draws out the electromotive force of the solar cell. Note that at point A, VB z0S is small, and the second base layer 11 and the light receiving part emitter layer 10
It is less effective in causing a forward voltage drop between the two.
一方、０点では、Ｉｐが小さいために、１、とは逆方向
の電子注入による電流で抵抗Ｒを流れるみかけの１．の
電流が更に小さくなシ、抵抗Ｒによる順方向の電圧降下
が小さくなる。以上の理由からＡ点およびＣ点付近では
光感度が低下する。On the other hand, at point 0, since Ip is small, an apparent current of 1. As the current becomes smaller, the voltage drop in the forward direction due to the resistor R becomes smaller. For the above reasons, photosensitivity decreases near points A and C.
この実施例によれば、最小点弧光入力ＰａＴが極小値と
なるＢ点では、抵抗層を付加しない時に比較して、光感
度を約３０％向上できることが、実験で確認できた。According to this example, it was experimentally confirmed that at point B, where the minimum ignition light input PaT is at its minimum value, the photosensitivity can be improved by about 30% compared to when no resistive layer is added.
第５図は、本発明の他の実施例を示すもので、抵抗Ｒを
光サイリスタ内に形成した点に特徴がある。抵抗層５０
０は、例えば抵抗率の制御が比較的容易な多結晶シリコ
ンによ多形成され、ｗｃｌ及び第２の電極２０２と２０
３によシ、第２ベース層１１と受光部エミツタ層１０Ｂ
とにそれぞれ低抵抗で接触している。４００は、第２ベ
ース層１１と受光部エミツタ層１０ｇとの短絡を防ぐた
（１０）
めのｓ ｓ ０２などの絶縁層である。FIG. 5 shows another embodiment of the present invention, which is characterized in that the resistor R is formed within the optical thyristor. resistance layer 50
0 is formed of, for example, polycrystalline silicon whose resistivity is relatively easy to control, and is connected to wcl and the second electrodes 202 and 20.
3, the second base layer 11 and the light receiving part emitter layer 10B
and are in contact with each other with low resistance. 400 is an insulating layer such as s s 02 (10) for preventing short circuit between the second base layer 11 and the light receiving portion emitter layer 10g.
このように抵抗Ｒも集積化すれば、外付は抵抗が不要と
なるので、スペースの節約となり、取扱いも容易である
。If the resistor R is also integrated in this manner, no external resistor is required, which saves space and facilitates handling.
第６図は、本発明のもうひとつの実施例を示している。FIG. 6 shows another embodiment of the invention.
この実施例では、第２図の抵抗Ｒと等価的な抵抗Ｒｚを
受光部エミツタ層内に設けたことを特徴とする。ｎ型導
電性の受光部エミツタ層１０ａは、電子の注入効率を良
くするために、一般に高濃度のキャリアを含んでおり、
抵抗率が小さくなっている。そこで、この受光部エミツ
タ層内に抵抗Ｒと等価な抵抗Ｒｚを設けるには、第６図
示の如く、受光部エミツタ層の一部をエツチングしてキ
ャリア数が少なく抵抗の大きな領域を形成すればよい。This embodiment is characterized in that a resistor Rz equivalent to the resistor R in FIG. 2 is provided in the emitter layer of the light receiving section. The n-type conductive light receiving emitter layer 10a generally contains a high concentration of carriers in order to improve electron injection efficiency.
Resistivity is low. Therefore, in order to provide a resistance Rz equivalent to the resistance R in the light-receiving emitter layer, a part of the light-receiving emitter layer is etched to form a region with a small number of carriers and a large resistance, as shown in Figure 6. good.
本実施例では、第５図に示すような抵抗層５００を形成
する必要がなく、製造が容易になる利点がある。This embodiment has the advantage that it is not necessary to form a resistance layer 500 as shown in FIG. 5, and manufacturing becomes easy.
なお、ｄｖ／ｄｔ耐量についての要求がそれほど厳しく
ｋい光サイリスタでは、上記抵抗層ＲＩＩを調整しても
よいことはいうまでもない。It goes without saying that in the case of an optical thyristor with very strict requirements for dv/dt withstand capability, the resistance layer RII may be adjusted.
（１１）
〔発明の効果〕
本発明によれば、太陽電池効果により発生する起電力を
効率よく引き出すために第２ペース層と受光部エミツタ
層との間に抵抗層を設けて光感度を高めることができ、
しかもこの抵抗層がｄ ｖ／ｄ ｉ耐量に対して何らの
悪影響を及ぼさないので、光感度が高くしかもｄ ｖ／
ｄ ｉ耐重も高い光半導体装置を得ることができる。(11) [Effects of the Invention] According to the present invention, in order to efficiently draw out the electromotive force generated by the solar cell effect, a resistance layer is provided between the second paste layer and the light-receiving part emitter layer to increase photosensitivity. It is possible,
Moreover, this resistive layer does not have any adverse effect on the d v/d i tolerance, so the photosensitivity is high and the d v/d
An optical semiconductor device with high di weight resistance can be obtained.
第１図は従来の光サイリスタの概略断面図、第２図は本
発明の第１実施例の概略断面図、第３図は抵抗と最小点
弧光入力の関係を示す特性図、第４図はベースとエミッ
タ間の市、圧と電流との関係を示す特性図、第５図は本
発明の第２実施例の概略断面図、第６図は本発明の第３
実施例の概略断面図である。
１・・・光半導体装置（光サイリスタ）、ｌｏ・・・ｎ
型導電性第２エミッタＭ、１０ ａ・・・受光部エミツ
タ層、１１・・・ｐ型導電性第２ベース層、１２・・・
ｎ型導電性第１ベース層・ １３・・・ｐ型導電性第１
エミ（１２）
ツタ層、２１・・・アノード電極、３０・・・光ファイ
バ、３１・・・光、２００・・・カソード電極、２０１
・・・受光部電極、２０２，２０３・・・第１．第２の
電極、４００・・・絶縁層、５００・・・抵抗層、Ｒ，
ＲＩ・・・抵抗。
代理人 弁理士 鵜沼辰之
（１３）
帛 ｌ 目
茅３ 目
ヘース・エミンタ向めｆｉ−”ｂ ％ニア九尺第 ５
日
第 ６ 日
３０２０！
３’ １０（Ｌ
；″
Ｊ３／ｌ
＝
丁Ｌ？ Ｔ／１２−一−−−トーー丁り、、ｒｈ、２１
丁 １１
Ｊｌ ” ＼１３Fig. 1 is a schematic sectional view of a conventional optical thyristor, Fig. 2 is a schematic sectional view of the first embodiment of the present invention, Fig. 3 is a characteristic diagram showing the relationship between resistance and minimum firing light input, and Fig. 4 is a schematic sectional view of a conventional optical thyristor. A characteristic diagram showing the relationship between voltage, voltage and current between the base and emitter, FIG. 5 is a schematic sectional view of the second embodiment of the present invention, and FIG. 6 is the third embodiment of the present invention.
It is a schematic sectional view of an example. 1... Optical semiconductor device (optical thyristor), lo...n
type conductive second emitter M, 10a...light receiving part emitter layer, 11...p type conductive second base layer, 12...
N-type conductive first base layer 13...p-type conductive first base layer
Emi (12) Ivy layer, 21... Anode electrode, 30... Optical fiber, 31... Light, 200... Cathode electrode, 201
. . . Light receiving part electrode, 202, 203 . . . 1st. Second electrode, 400... Insulating layer, 500... Resistance layer, R,
RI...Resistance. Agent Patent attorney Tatsuyuki Unuma (13) 3rd page for Hess Eminta fi-”b %Nia Nine Shaku No. 5
Day 6th 3020! 3'10(L;'' J3/l = Ding L? T/12-1--To-Ding,, rh, 21 Ding 11 Jl" \13
Claims (1)
層、第２ベース層、第２エミッタ層の積層からなる主サ
イリスタ領域と、第１エミッタ層。 第１ペース層、第２ベース層及び受光部エミツタ層の積
層からなる受光部サイリスタ領域とが並設された半導体
基体と、第１エミッタ層にオーミックコンタクトした第
１の主電極と、第２エミッタ層にオーミックコンタクト
した第２の主電極と、受光部エミツタ層表面に光ｌ・リ
ガー信号を付与する手段と、受光部エミツタ層と第２ペ
ース層との間に、光トリガ信号を付与したときに第２ペ
ース層と受光部エミツタ層との間に発生する光起電力を
最大にする抵抗値を有する抵抗分と、を形成したことを
特徴とする光半導体装Ｉｆｆ。 ２、特許請求の範囲第１項において、抵抗分が前記短絡
部に介在させた外付は抵抗であることを特徴とする光半
導体装置。 ３、特許請求の範囲第１項において、抵抗分を前記半導
体基体内の第１領域自体に形成したことを特徴とする光
半導体装置。[Claims] 1. A main thyristor region and a first emitter layer consisting of a stack of a first emitter layer, a first space layer, a second base layer, and a second emitter layer of alternating conductivity types. A semiconductor substrate in which a light-receiving part thyristor region consisting of a laminated layer of a first space layer, a second base layer, and a light-receiving part emitter layer are arranged in parallel, a first main electrode in ohmic contact with the first emitter layer, and a second emitter layer. When an optical trigger signal is applied between the second main electrode in ohmic contact with the layer, the means for applying a light trigger signal to the surface of the light receiving part emitter layer, and the light receiving part emitter layer and the second paste layer. and a resistor having a resistance value that maximizes the photovoltaic force generated between the second paste layer and the light-receiving part emitter layer. 2. The optical semiconductor device according to claim 1, wherein the external component interposed in the short-circuit portion is a resistor. 3. An optical semiconductor device according to claim 1, characterized in that a resistance portion is formed in the first region itself within the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58202208A JPS6094768A (en) | 1983-10-28 | 1983-10-28 | Photosemiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58202208A JPS6094768A (en) | 1983-10-28 | 1983-10-28 | Photosemiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6094768A true JPS6094768A (en) | 1985-05-27 |
Family
ID=16453749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58202208A Pending JPS6094768A (en) | 1983-10-28 | 1983-10-28 | Photosemiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6094768A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH041916A (en) * | 1990-03-12 | 1992-01-07 | Toshiba Corp | Semiconductor device |
-
1983
- 1983-10-28 JP JP58202208A patent/JPS6094768A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH041916A (en) * | 1990-03-12 | 1992-01-07 | Toshiba Corp | Semiconductor device |
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