JPS609355U - phase modulation circuit - Google Patents
phase modulation circuitInfo
- Publication number
- JPS609355U JPS609355U JP9949283U JP9949283U JPS609355U JP S609355 U JPS609355 U JP S609355U JP 9949283 U JP9949283 U JP 9949283U JP 9949283 U JP9949283 U JP 9949283U JP S609355 U JPS609355 U JP S609355U
- Authority
- JP
- Japan
- Prior art keywords
- output
- input terminal
- signal
- modulation circuit
- phase modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の位相変調回路、第２図は本考案の一実施
例のブロック図、第３図は第２図の要部の一例の構成説
明図、第４図は動作説明図、第５図は本考案の他の実施
例のブロック図、第６図はその動作説明図である。
１は入力端子、２は混合器、３は出力端子、４はキャリ
ア発振器、５は検波器、６はアナログスイッチ、７はピ
ーク検出器、８は差動増幅器、９は積分−ｍ、ｔｏは比
較器、ｃｌ、ｃ２はコンデンサ、Ｄ、Ｃ，ＣＡＲ，ＯＵ
Ｔは、それぞれ混合器２のディジタル信号の入力端子、
制御信号の入力端子、キャリア信号の入力端子及び位相
変調信号の出力端子である。Fig. 1 is a conventional phase modulation circuit, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the configuration of an example of the main part of Fig. 2, Fig. 4 is an explanatory diagram of the operation, FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is an explanatory diagram of its operation. 1 is an input terminal, 2 is a mixer, 3 is an output terminal, 4 is a carrier oscillator, 5 is a detector, 6 is an analog switch, 7 is a peak detector, 8 is a differential amplifier, 9 is an integral -m, and to is Comparator, cl, c2 are capacitors, D, C, CAR, OU
T are the input terminals of the digital signal of the mixer 2, respectively;
These are an input terminal for a control signal, an input terminal for a carrier signal, and an output terminal for a phase modulation signal.
Claims (1)
リア信号の入力端子と平衡調整用の制御信号の入力端子
と位相変調信号の出力端子とを有する混合器、該混合器
の出力端子からの位相変調信号を検波する検波器、該検
波器の出力の前記ディジタル信号の“１′に対応する出
力と０１９に対応する出力とを切換出力するアナログス
イッチ、該アナログスイッチの２個の出力をそれぞれピ
ーク検出器、該ピーク検出器の２個の出力を比較する差
動増幅器、該差動増幅器の出力を積分して前記混合器の
平衡調整用の制御信号とする積分器とを備えたことを特
徴とする位相変調回路。A mixer having an input terminal for a digital signal, an input terminal for a carrier signal from a carrier oscillator, an input terminal for a control signal for balance adjustment, and an output terminal for a phase modulation signal; A wave detector for detecting the wave, an analog switch for switching and outputting an output corresponding to “1” and an output corresponding to 019 of the digital signal of the output of the wave detector, and a peak detector for each of the two outputs of the analog switch, A phase shifter characterized by comprising: a differential amplifier that compares two outputs of the peak detector; and an integrator that integrates the output of the differential amplifier to provide a control signal for adjusting the balance of the mixer. Modulation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9949283U JPS609355U (en) | 1983-06-29 | 1983-06-29 | phase modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9949283U JPS609355U (en) | 1983-06-29 | 1983-06-29 | phase modulation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS609355U true JPS609355U (en) | 1985-01-22 |
Family
ID=30235755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9949283U Pending JPS609355U (en) | 1983-06-29 | 1983-06-29 | phase modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609355U (en) |
-
1983
- 1983-06-29 JP JP9949283U patent/JPS609355U/en active Pending
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