JPS6092634A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6092634A JPS6092634A JP20038183A JP20038183A JPS6092634A JP S6092634 A JPS6092634 A JP S6092634A JP 20038183 A JP20038183 A JP 20038183A JP 20038183 A JP20038183 A JP 20038183A JP S6092634 A JPS6092634 A JP S6092634A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- insulating film
- nitrogen
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(1) 発明の属する技術分野の説明
本発明は半導体装置の多層配線構造における眉間絶縁膜
の形成方法及び該眉間絶縁膜への。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a method for forming a glabellar insulating film in a multilayer wiring structure of a semiconductor device, and a method for forming the glabellar insulating film.
眉間スルーホールの形成方法に関スル。About how to form a through hole between the eyebrows.
(2)従来技術の説明
従来、この種の半導体装置における層間絶縁膜へのスル
ーホール形成におりては、パターンの微細化にともない
、スルーホールエッジテノ上層配線の段切れ防止の為1
等方性工、チングと異方性エツチングの2ステツプの工
、チングによる加工が行われている。この時従来技術に
よる眉間絶縁膜及びスルーポール形成方法では最初のス
テップにおけるエツチング量の検出及びコントロールが
十分できないという欠点がありた・
(3)発明の詳細な説明
不発明は上記欠点を解決する為に1層間絶縁膜として用
いる窒化膜中に1サンドイツf構造で窒素を含まない層
全工、チングマーカーとして入れ、窒素の発光スペクト
ルをモニターしながら等方的にプラズマドライエ、チン
グすることによって、マーカ一層までt正確にエッチン
ブレ、残膜の膜厚全−足化し、残膜を異方性エツチング
することにより再現性のよいスルーホール形状’kA供
するものである・
本発明の一態様においては、基板上に形成された下層配
線上に第1の絶縁膜としてのプラズマCVD窒化膜、第
2の絶縁膜としての窒素を含まないエツチングマーカー
としての絶縁膜。(2) Description of the prior art Conventionally, when forming through holes in the interlayer insulating film of this type of semiconductor device, as the pattern becomes finer, it is necessary to
Processing using isotropic etching, a two-step process of etching and etching, and etching are performed. At this time, the method of forming the glabella insulating film and through-pole according to the prior art had the drawback that the amount of etching could not be detected and controlled sufficiently in the first step. (3) Detailed Description of the Invention The purpose of the invention is to solve the above drawbacks. In the nitride film used as the interlayer insulating film, a layer containing no nitrogen with a 1-Sand German f structure was added as a etch marker, and the nitrogen emission spectrum was monitored while being isotropically plasma-dried and etched. In one embodiment of the present invention, a through-hole shape with good reproducibility is provided by accurately etching up to the marker layer, reducing the remaining film thickness to the full thickness, and anisotropically etching the remaining film. , a plasma CVD nitride film as a first insulating film on the lower wiring formed on the substrate, and an insulating film as an etching marker that does not contain nitrogen as a second insulating film.
第3の絶縁膜としてのプラズマCVDM化膜の3層構造
を有゛3−る層間絶縁膜全形成し、プラズマドライエツ
チングで窒素の発光スペクトルをモニターしながら第3
の絶縁膜としてのプラズマCVD窒化膜を等方性エツチ
ングし、第2の絶縁膜としてQ室累を含まない絶縁膜及
び第1の絶縁膜としてのプラズマCVD窒化膜を連続又
は別々に異方性エツチングして層間絶縁膜にスルーホー
ルを形成する。An interlayer insulating film having a three-layer structure of a plasma CVDM film as a third insulating film is completely formed, and the third insulating film is etched while monitoring the emission spectrum of nitrogen by plasma dry etching.
The plasma CVD nitride film as the insulating film is isotropically etched, and the second insulating film is an insulating film that does not contain Q chambers, and the first insulating film is anisotropically etched. A through hole is formed in the interlayer insulating film by etching.
(4)この発明の詳細な説明 次に本発明の実施例について図面を参照して説明する。(4) Detailed description of this invention Next, embodiments of the present invention will be described with reference to the drawings.
第1図及至第3図は各々スルーホール形成に至る工程の
スルーホール部と下層配線及び眉間絶縁膜の断面図全ボ
したものであり。1 to 3 are fully blown cross-sectional views of the through-hole portion, lower layer wiring, and glabella insulating film in the process leading to through-hole formation, respectively.
本発明を用いて2ステ、プエ、チング?行いスルーホー
ル全形成した実施例である。第1図に示すように下層配
線4上にプラズマCvDM化膜l、輩素を含まない絶縁
膜(例えば5iOz)2、プラズマCVD窒化膜3の3
層構造の絶縁膜全形成し、フォトレジスト5にてスルー
ホールパターンを形成する1次に第2図に示すようにプ
ラズマCVD窒化膜3をプラズマドライエツチングにて
等方性エツチングする。その際窒素の発光スペクトルを
モニターすることによって窒素を含まない絶縁膜2TI
c達するところでプラズマCVD窒化膜3のエツチング
終点を検出し、工、チング全止めることができる・こう
して穴6をあける0次に第3図に示すように窒素を含ま
ない絶縁膜2.及びプラズマCVD窒化膜1を異方性エ
ツチングにてエツチングし、これによってテーバを持っ
たスルーホール7を形成して下層配線の一部を露出させ
る。2 steps, pue, ching using this invention? This is an example in which all through holes were formed. As shown in FIG. 1, on the lower wiring 4 are a plasma CVDM film 1, an insulating film (for example, 5 iOz) 2 that does not contain a stimulant, and a plasma CVD nitride film 3.
After forming the entire layered insulating film and forming a through hole pattern using photoresist 5, the plasma CVD nitride film 3 is isotropically etched by plasma dry etching as shown in FIG. At that time, by monitoring the emission spectrum of nitrogen, the insulating film 2TI that does not contain nitrogen is
The etching end point of the plasma CVD nitride film 3 can be detected at the point where the plasma CVD nitride film 3 is reached, and the etching can be completely stopped. Then, the plasma CVD nitride film 1 is etched by anisotropic etching, thereby forming a tapered through hole 7 and exposing a portion of the underlying wiring.
(5)発明の詳細な説明
本発明は以上説明したように被エツチング窒化膜中にエ
ツチングマーカーとして、窒素を含まない膜をはさみ、
これによるプラズマエツチング中のN2発光スペクトル
全モニターすることによって工、チング量をコントロー
ルし、残膜の膜厚を一足化できる効果がある。(5) Detailed Description of the Invention As explained above, the present invention comprises sandwiching a nitrogen-free film as an etching marker in a nitride film to be etched,
By monitoring the entire N2 emission spectrum during plasma etching, the amount of etching can be controlled and the thickness of the remaining film can be reduced.
第1図乃至第3図は本発明の実施の断面図である。
1・・・・・・プラズマCVD窒化膜、2・・・・・・
窒素を含まない絶縁膜(例えば5i(J2)、3・・・
・・−プラズマCVD窒化膜、4・・・・・・下層配線
、5・・・・・・フォトレジスト、6・・・・・・窒素
の発光スペクトルをモニターしてエツチングした部分、
7・山・・本発明にょる2ステツプエツチングによって
形成されるスルーホール。1-3 are cross-sectional views of an implementation of the present invention. 1... Plasma CVD nitride film, 2...
Insulating film that does not contain nitrogen (e.g. 5i (J2), 3...
...-plasma CVD nitride film, 4...lower wiring, 5...photoresist, 6...portion etched by monitoring nitrogen emission spectrum,
7. Mountain: Through hole formed by two-step etching according to the present invention.
Claims (1)
化膜、第2の絶縁膜として窒素を含まない工、チングマ
ーカーとしての絶縁膜、第3の絶縁膜として窒化膜の3
層構造を有する層間絶縁膜を形成する工程と、プラズマ
ドライエ、チングで室累の発光スペクトルをモニターし
ながら前記第3の絶縁膜を、等方性エツチングする工程
と、前記第2の絶縁膜及び前記第1の絶縁膜を連続又は
別々に異方性エツチングする工程とを有することを特徴
とする半導体装置の製造方法。A nitride film as a first insulating film, a nitrogen-free film as a second insulating film, an insulating film as a marking marker, and a nitride film as a third insulating film are formed on the lower wiring formed on the substrate.
a step of forming an interlayer insulating film having a layered structure; a step of isotropically etching the third insulating film while monitoring the emission spectrum of the chamber by plasma drying and etching; and a step of isotropically etching the third insulating film. and a step of anisotropically etching the first insulating film successively or separately.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20038183A JPS6092634A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20038183A JPS6092634A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6092634A true JPS6092634A (en) | 1985-05-24 |
Family
ID=16423371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20038183A Pending JPS6092634A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6092634A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62174945A (en) * | 1986-01-28 | 1987-07-31 | Rohm Co Ltd | Formation of interconnection for semiconductor device |
JPS6420677A (en) * | 1987-07-16 | 1989-01-24 | Agency Ind Science Techn | Manufacture of josephson junction |
JPH01295423A (en) * | 1987-08-14 | 1989-11-29 | Fairchild Semiconductor Corp | Etching back detection |
-
1983
- 1983-10-26 JP JP20038183A patent/JPS6092634A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62174945A (en) * | 1986-01-28 | 1987-07-31 | Rohm Co Ltd | Formation of interconnection for semiconductor device |
JPS6420677A (en) * | 1987-07-16 | 1989-01-24 | Agency Ind Science Techn | Manufacture of josephson junction |
JPH01295423A (en) * | 1987-08-14 | 1989-11-29 | Fairchild Semiconductor Corp | Etching back detection |
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