JPS609211U - inductance element - Google Patents

inductance element

Info

Publication number
JPS609211U
JPS609211U JP9982683U JP9982683U JPS609211U JP S609211 U JPS609211 U JP S609211U JP 9982683 U JP9982683 U JP 9982683U JP 9982683 U JP9982683 U JP 9982683U JP S609211 U JPS609211 U JP S609211U
Authority
JP
Japan
Prior art keywords
intermediate layer
conductive pattern
inductance element
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9982683U
Other languages
Japanese (ja)
Inventor
誠一 竹野
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP9982683U priority Critical patent/JPS609211U/en
Publication of JPS609211U publication Critical patent/JPS609211U/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第6図は、この考案の一実施例を得るため
の工程を順次示す。第7図ないし第10図はこの考案の
他の実施例を得るための工程を順次示す。第11図は基
板1上における引出電極2の形成態様の好ましい例を示
す。 図において、1,13は基板、2. 3. 14゜15
は引出電極、4. 5. 8. 9. 11. 16゜
17.19は導電パターン、4a、  5a、  3a
、  9a。 16a、17aは導電パターンの終端部、6,10゜1
8は中間層、12.20は上面層である。
1 to 6 sequentially show steps for obtaining an embodiment of this invention. 7 to 10 sequentially show steps for obtaining another embodiment of this invention. FIG. 11 shows a preferred example of the formation of the extraction electrode 2 on the substrate 1. In the figure, 1 and 13 are substrates, 2. 3. 14°15
is an extraction electrode; 4. 5. 8. 9. 11. 16゜17.19 are conductive patterns, 4a, 5a, 3a
, 9a. 16a and 17a are the terminal ends of the conductive pattern, 6, 10°1
8 is the middle layer, and 12.20 is the top layer.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)ベースとなる磁性または絶縁性の基板と、前記基
板の端部の互いに異なる位置にそれぞれ形成される1対
の引出電極と、 インダクタンス成分を作り出す導電経路の一部をなすよ
うに前記各引出電極からそれぞれ出発して前記基板上に
形成される第1および第2の導電パターンと、− 前記各引出電極を露出させた状態で前記基板上に積層き
れる少なくとも1層の中間層と、前記中間層上に形成さ
れ、前記第1および第2の導電パターンの各終端部を互
いに導電的に接続する第3の導電パターンと、 前記各引出電極を露出させた状態で前記中間層の上方に
積層される上面層とを備え、前記中間層はその下にある
導電パターンの終端部を露出させる状態に積層され、こ
の下にある導電パターンはこの露出された面において当
該中間層の上に形成された導電パターンと導電的に接続
され、かつ 前記中間層および上面層は、磁性または絶縁性セラミッ
ク材料の焼結済粉末を含むペーストを固体化して得られ
たものである、インダクタンス素子。
(1) A magnetic or insulating substrate serving as a base, a pair of extraction electrodes formed at mutually different positions on the edge of the substrate, and each of the aforementioned first and second conductive patterns formed on the substrate starting from extraction electrodes, respectively; - at least one intermediate layer that can be laminated on the substrate with each extraction electrode exposed; a third conductive pattern formed on the intermediate layer and electrically connecting the terminal ends of the first and second conductive patterns to each other; and a third conductive pattern formed above the intermediate layer with each of the lead electrodes exposed. a top layer to be laminated, the intermediate layer being laminated to expose a terminal end of a conductive pattern thereunder, and the underlying conductive pattern being formed on the intermediate layer on the exposed surface; an inductance element, wherein the intermediate layer and the top layer are obtained by solidifying a paste containing sintered powder of a magnetic or insulating ceramic material.
(2)前記中間層は1層だけ形成され、前記第3の導電
パターンは、この1層の中間層上に形成される、実用新
案登録請求の範囲第(1)項記載のインダクタンス素子
(2) The inductance element according to claim 1, wherein only one intermediate layer is formed, and the third conductive pattern is formed on this one intermediate layer.
(3)  前記中間層は複数層形成され、前記第3の導
電パターンは、複数層の中間層のうち最上部に位置する
ものを除く中間層上にそれぞれ2つずつ形成される導電
パターンと、最上部に位置する中間層上に形成される1
つの導電パターンとを含む、実用新案登録請求の範囲第
(1)項記載のインダクタンス素子。
(3) The intermediate layer is formed in a plurality of layers, and the third conductive pattern is formed in two conductive patterns on each of the intermediate layers except for the uppermost one among the plurality of intermediate layers; 1 formed on the middle layer located at the top
The inductance element according to claim (1), which comprises two conductive patterns.
JP9982683U 1983-06-28 1983-06-28 inductance element Pending JPS609211U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9982683U JPS609211U (en) 1983-06-28 1983-06-28 inductance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9982683U JPS609211U (en) 1983-06-28 1983-06-28 inductance element

Publications (1)

Publication Number Publication Date
JPS609211U true JPS609211U (en) 1985-01-22

Family

ID=30236406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9982683U Pending JPS609211U (en) 1983-06-28 1983-06-28 inductance element

Country Status (1)

Country Link
JP (1) JPS609211U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426325U (en) * 1987-08-03 1989-02-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426325U (en) * 1987-08-03 1989-02-14

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