JPS6091696A - Method of producing hybrid integrated circuit device - Google Patents

Method of producing hybrid integrated circuit device

Info

Publication number
JPS6091696A
JPS6091696A JP20175283A JP20175283A JPS6091696A JP S6091696 A JPS6091696 A JP S6091696A JP 20175283 A JP20175283 A JP 20175283A JP 20175283 A JP20175283 A JP 20175283A JP S6091696 A JPS6091696 A JP S6091696A
Authority
JP
Japan
Prior art keywords
region
integrated circuit
hybrid integrated
circuit device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20175283A
Other languages
Japanese (ja)
Inventor
中川 興一
晴夫 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20175283A priority Critical patent/JPS6091696A/en
Publication of JPS6091696A publication Critical patent/JPS6091696A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、混成集積回路装置の製造方法に関するもの
で61、特に絶縁基板の画工面に導体配線?有する混成
集積回路装置の製造方法に関するものでるる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a hybrid integrated circuit device, and particularly relates to a method for manufacturing a hybrid integrated circuit device. This article relates to a method for manufacturing a hybrid integrated circuit device having the following.

〔従来技術〕[Prior art]

この種の混成集積回路装置の構造及び従来からの製造方
法を第1回の斜視図及び第2図の側断面図を用いて説明
する。まず、セラミック等からなる絶縁基板1の両生面
に銀パラジウムや金などの導体ペースト、酸化ルテニウ
ムなどの抵抗ペーストるるいはガラスなどの絶縁ペース
トをスクリーン印刷法によシ所定の形状に印刷し焼成す
る。次に導体ペーストを焼成することによシ形成された
印刷導体2にチップコンデンサ3や半導体素子4などを
半日または導電性接着剤を用いて実装した後、クリップ
リード5を絶縁基板1上のリード接続用電極6に取り付
ける。その後回路の電気特性を検査する。このとき、製
品によっては印刷抵抗体7をレーザなどの手段によって
トリミングしながら電気的特性?調整する。その後必要
がろれは外装樹脂8全被覆する。
The structure and conventional manufacturing method of this type of hybrid integrated circuit device will be explained using a first perspective view and a side sectional view in FIG. First, a conductive paste such as silver palladium or gold, a resistive paste such as ruthenium oxide, or an insulating paste such as glass is printed in a predetermined shape using a screen printing method on both sides of an insulating substrate 1 made of ceramic or the like, and then fired. do. Next, chip capacitors 3, semiconductor elements 4, etc. are mounted on the printed conductor 2 formed by firing the conductive paste for half a day or using a conductive adhesive, and then the clip leads 5 are attached to the leads on the insulating substrate 1. Attach to the connection electrode 6. The electrical characteristics of the circuit are then inspected. At this time, depending on the product, the printed resistor 7 may be trimmed using a laser or other means to check the electrical characteristics. adjust. After that, cover the entire exterior resin 8 to cover any necessary leakage.

ここにおけるクリップリード5は単に回路の入出力端子
としての役割を有するだけでなく、スルーホール配線9
と同様に表の配線と裏の配線とを電気的に接続する役割
をも有する。これはクリップリード5にスルーホール配
線と同等の役割tもたせて、回路内のスルーホール配線
数を極力少なくシ、小型高密度化全型む市場のニーズに
応えんとするものでるる。
The clip lead 5 here not only has a role as an input/output terminal of the circuit, but also has a role as a through-hole wiring 9.
Similarly, it also has the role of electrically connecting the front wiring and the back wiring. This is intended to allow the clip lead 5 to play the same role as through-hole wiring, to minimize the number of through-hole wiring in the circuit, and to meet the needs of the market for all types of compact, high-density circuits.

ところかクリップリード5にスルーホール配線の役割を
付加したことから、回路の電気特性の調整・検査をクリ
ップリード5を取り付けた後でなければ行なえないとい
う事態が生じた。製造工程の歩留を考えれば、このよう
な事態は望ましくなく、どうしてもクリップリード5t
−取り付ける前に電気特性の調整・検査を終了させ検査
をパスしたものについてのみクリップリードを取シ付け
たい。もちろん、測定用プローブ針全絶縁基板1の両面
から同時に当てるなどしてクリップリード5を取り付け
る前に測定することは不可能ではないが、量産過程の中
で簡易に行なう必要かめるこの種の検査には適当でない
However, since the role of through-hole wiring was added to the clip lead 5, a situation arose in which the electrical characteristics of the circuit could only be adjusted and inspected after the clip lead 5 was attached. Considering the yield of the manufacturing process, this situation is undesirable, and it is necessary to use clip leads of 5 tons.
- I would like to install clip leads only on products that have completed the adjustment and inspection of electrical characteristics before installation and have passed the inspection. Of course, it is not impossible to measure before attaching the clip lead 5 by applying the measurement probe needle to both sides of the fully insulated board 1 at the same time, but this type of inspection is not possible because it is easily necessary during the mass production process. is not appropriate.

〔発明の概要〕[Summary of the invention]

本発明は上記問題点に鑑みてなされたものでろり、その
目的とするところは、基板両面に導体配mを有し、クリ
ップリードによって両面の導体の電気的接続を為さしめ
ている混成集積回路装置の製造過程において、クリップ
リードを取り付ける前に極めて簡単に電気特性の調整・
検査全行なうことのできる製造方法?提供することにる
る。
The present invention has been made in view of the above-mentioned problems, and its object is to provide a hybrid integrated circuit having conductor distribution m on both sides of a substrate and electrically connecting the conductors on both sides with clip leads. During the device manufacturing process, electrical characteristics can be adjusted and adjusted very easily before clip leads are attached.
Is there a manufacturing method that allows full inspection? It depends on providing.

この目的全達成するために、本発明は、半導体素子等を
実装する第1の領域とスルーホール配線が施される第2
の領域とに基板を区分し、実装及び配線完了後に電気特
性の調整・検査を行ない、その後前記第2の領域を分離
除去するとともに第1の領域にクリップリードを取り付
けるものである。
In order to achieve all of these objects, the present invention provides a first region for mounting semiconductor elements and the like and a second region for mounting through-hole wiring.
After completing the mounting and wiring, the board is divided into two regions, and the electrical characteristics are adjusted and inspected.The second region is then separated and removed, and a clip lead is attached to the first region.

〔発明の実施例〕[Embodiments of the invention]

以下実施例とともに本発明の詳細な説明する。 The present invention will be described in detail below along with examples.

第3図は、本発明の製造方法の一過程を示す平面図でめ
り、第4図はそのA−A’断面図である。
FIG. 3 is a plan view showing one process of the manufacturing method of the present invention, and FIG. 4 is a sectional view taken along the line AA'.

なお、第1図又は第2図における構成要素と同−又は類
似の要素には同一の符号を付してるる。
In addition, the same reference numerals are given to the same or similar elements as those in FIG. 1 or 2.

絶縁基板1に基板厚みの約2分の1ないし3分の1の深
さの切り溝10を設ける。その後絶縁基板1の両面に導
体ペースト15.抵抗ペースト16ろるいは図示しない
絶縁ペースト等を印刷し焼成する。このとき、切り溝1
0で仕切られた一方の領域11には将来半導体素子等が
実装されるべく配線が形成されるとともに、切り#11
0の近傍にはクリップリードを接続するための電極6が
形成される。また、他方の領域13には、電極6をさら
に延長した配線を施し、その末端部14にはスルーホー
ル配線17t−形成する。
A cut groove 10 having a depth of about 1/2 to 1/3 of the substrate thickness is provided in an insulating substrate 1. After that, conductor paste 15. Resistance paste 16 or an insulating paste (not shown) is printed and fired. At this time, kerf 1
In one area 11 partitioned by 0, wiring is formed so that semiconductor elements etc. will be mounted in the future.
An electrode 6 for connecting a clip lead is formed near point 0. Further, in the other region 13, a wiring further extending from the electrode 6 is provided, and a through-hole wiring 17t is formed at the end portion 14 of the wiring.

次に領域11にチップコンデンサや半導体素子等を半日
または導電性接着剤によって実装すると、基板1の画工
面に形成された導体配線間の電気的、接続はすでにスル
ーホール配線11により完了しているので、最終的に必
要な回路が完成したことによる。したがって、この段階
で回路の電気特性の測定を片面に測定用のグローブ針を
当てるだけで行なうことができる。
Next, when a chip capacitor, a semiconductor element, etc. is mounted in the area 11 for half a day or with a conductive adhesive, the electrical connection between the conductor wiring formed on the drawing surface of the substrate 1 is already completed by the through-hole wiring 11. Therefore, the necessary circuit was finally completed. Therefore, at this stage, the electrical characteristics of the circuit can be measured simply by applying a measuring glove needle to one side.

測定終了後は第5図に示すように、切シ溝10を利用し
て基板1の領域13を領域11から機械的に割って分離
する。このとき、基板の表裏に施された導体の電気的接
続か一旦切断される仁とになるが、次の段階でクリップ
リード全電極6に対応させて取り付けることにより、再
び導通することになる。その後は必要に応じて外装樹脂
を被覆し混成集積回路装置が完成する。
After the measurement is completed, as shown in FIG. 5, the region 13 of the substrate 1 is mechanically separated from the region 11 using the cutting groove 10. At this time, the electrical connections between the conductors on the front and back sides of the substrate are temporarily cut off, but in the next step, the clip leads are attached in correspondence with all the electrodes 6, and conduction is established again. Thereafter, the hybrid integrated circuit device is completed by covering with an exterior resin as necessary.

なお、本実施例では、めらかしめ切り溝を施して、スル
ーホール配線領域を簡単に除去できるようにしているが
、他の切断手段を利用してもよいことはもちろんでるる
In this embodiment, smooth cutting grooves are provided so that the through-hole wiring area can be easily removed, but it is of course possible to use other cutting means.

第6図は第2の実施例を示す平面図でるる。ここでは絶
縁基板1を切り溝23.24によって20ないし22の
3領域に仕切り、各領域において表裏一体となったそれ
ぞれ独立の回路が形成される。
FIG. 6 is a plan view showing the second embodiment. Here, the insulating substrate 1 is partitioned into three areas 20 to 22 by grooves 23 and 24, and independent circuits are formed in each area, with the front and back sides integrated.

20ないし22の各領域で杜、前記した第1の実施例の
ように切ジ溝25ないし21によってそれぞれ実装領域
Aとスルーホール配線領域Bとに区分される。領域20
ないし22にそれぞれ形成される回路は同種類のもので
もよいし異種類のものでもよい。
Each region 20 to 22 is divided into a mounting region A and a through-hole wiring region B by grooves 25 to 21, respectively, as in the first embodiment. area 20
The circuits formed in each of the circuits 22 to 22 may be of the same type or may be of different types.

この基板1に、導体等の配線を施した後、半導体素子等
の実装作業さらに電気特性測定作業を行なう。その後切
シ溝23ないし27全利用して分割し、各実装領域にク
リップリード?取り付けて混成集積回路装置が完成する
。このようにすると作業中のハンドリング時間が短縮さ
れ生産性の向上を図ることができる。
After wiring such as conductors is provided on this substrate 1, work for mounting semiconductor elements and the like and work for measuring electrical characteristics are performed. After that, divide the cutting grooves 23 to 27 using all of them, and attach clip leads to each mounting area. Attach it to complete the hybrid integrated circuit device. In this way, handling time during work can be shortened and productivity can be improved.

なお、本実施例では、簡単のため3個の回路としている
が、必要に応じて2個以上何個でもかまわないことはい
うまでもない。
In this embodiment, there are three circuits for simplicity, but it goes without saying that the number of circuits may be two or more as required.

第7図は第3の実施例を示す平面図である。本実施例に
おいては、半導体素子等を実装する領域30は第1の実
施例と同一でるるか、スルーホール配線17を形成する
領域31における配線形状が異なるものである。すなわ
ち、スルーホール配線1Tが千鳥状に配列されているも
のである。スルーホール配線17の周囲にはランド32
がめるので、導体間の絶縁性を保証葡するための最小距
離Si考慮しスルーホール配線間の距離を十分とる必要
がるる。このときのスルーホール配線間i間の最小距離
t−Lとすると第8図に示すようにスルーホール配線1
Tを直線状に配列した場会には、リード接続用電極6の
ピッチPはスルーホール配線間の最小距離り以下にはな
らない。しかし本実施例によれば、第9図の部分拡大図
に示すように、スルーホール中心位置を寸法aだけ交互
にずらしているので、スルーホール配線間の最小距離り
全確保しつつリード接続用電極6のピッチPi距離り以
下とすることができる。これによってさらに装置を小型
高密度化することができる。
FIG. 7 is a plan view showing the third embodiment. In this embodiment, the area 30 for mounting semiconductor elements and the like is the same as the first embodiment, or the wiring shape in the area 31 for forming the through-hole wiring 17 is different. That is, the through-hole wiring 1T is arranged in a staggered manner. A land 32 is provided around the through-hole wiring 17.
Therefore, it is necessary to take into consideration the minimum distance Si to guarantee the insulation between the conductors and provide a sufficient distance between the through-hole wiring. If the minimum distance between the through-hole wirings i at this time is t-L, the through-hole wiring 1 as shown in FIG.
When the T's are arranged in a straight line, the pitch P of the lead connection electrodes 6 will not be less than the minimum distance between the through-hole wirings. However, according to this embodiment, as shown in the partially enlarged view of FIG. 9, the center positions of the through-holes are alternately shifted by the dimension a, so that the minimum distance between the through-hole wirings can be ensured while still allowing for lead connection. The pitch of the electrodes 6 can be set to be equal to or less than the distance Pi. This allows the device to be made smaller and more dense.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、基板両面に導体
配線を有しクリップリードによって両面の導体の電気的
接続を為さしめている混成集積回路装置の製造過程にお
いて、クリップリードによる電気的接続箇所にクリップ
リード取り付は前にスルーホール配線し、必要な素子v
i−実装した後電気特性の調整・検査を行ない、その後
スルーホール配線を除去してクリップリード全敗り付け
るので、クリップリードを取り付ける前でも極めて簡単
に電気特性の調整・検査を行なうことができる。
As explained above, according to the present invention, in the process of manufacturing a hybrid integrated circuit device that has conductor wiring on both sides of a substrate and uses clip leads to electrically connect the conductors on both sides, To attach the clip lead to the location, wire the through-hole in front and connect the necessary element v.
After i-mounting, the electrical characteristics are adjusted and inspected, and then the through-hole wiring is removed and all the clip leads are attached, so the electrical characteristics can be adjusted and inspected very easily even before attaching the clip leads.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は混成集積回路装置l金示す斜視図、第2図は第
1図の装置の側断面図、第3図は本発明の一実施例を示
す平面図、第4図は第3図のA −A’断面図、第5図
り第3図の基板を割った状態、を示す平面図、第6図は
第2の実施例を示す平面図、第7図は第3の実施例を示
す平面図、第8図は第3の実施例を説明するための図、
第9図は第7図の部分拡大図でろる。 1・0.拳絶縁基板、5.・・・クリップリード、6・
・・・リード接続用電極、10,23゜24.25.2
6.27・0・・切9溝、17・・e″スルーホール配
線 代理人 大岩増雄 第4図 第7図 第8図 第9図 手続補正書(自発) ↑、1−5′[庁長官殿 1、=lG件の表示 ↑1−願昭5B−201752号
2、発明の名称 混成集積回路装置の製造方法:3.補
正をする者 事件との関係 特許出願人 住 所 東j;〔都千代IJJ区丸の内二丁目2番3号
名 称 (601)三菱電機株式会社 代表者片由仁八部 4、代理人 明細書の発明の詳細な説明の欄 6、補正の内容
FIG. 1 is a perspective view showing a hybrid integrated circuit device, FIG. 2 is a side sectional view of the device shown in FIG. 1, FIG. 3 is a plan view showing an embodiment of the present invention, and FIG. Fig. 6 is a plan view showing the second embodiment, and Fig. 7 is a plan view showing the third embodiment. FIG. 8 is a diagram for explaining the third embodiment,
Figure 9 is a partially enlarged view of Figure 7. 1.0. Fist insulation board, 5. ...Clip lead, 6.
...Lead connection electrode, 10,23°24.25.2
6.27.0...cut 9 grooves, 17...e'' through hole wiring agent Masuo Oiwa Figure 4 Figure 7 Figure 8 Figure 9 Procedure amendment (voluntary) ↑, 1-5' [Agency Commissioner 1. Display of =lG ↑1-Application No. 5B-201752 2. Title of invention Method for manufacturing a hybrid integrated circuit device: 3. Relationship with the case of the person making the amendment Patent applicant address Higashij; [Tokyo 2-2-3 Marunouchi, Chiyo IJJ-ku Name (601) Mitsubishi Electric Corporation Representative Katayuni Part 8 Section 4 Detailed description of the invention in the agent's specification Column 6 Contents of the amendment

Claims (1)

【特許請求の範囲】 (i)絶縁基板を第1の領域と第2の領域に区分し、こ
の絶縁基板の画工面に導体配線を施し、前記第1の領域
には能動素子又は受動素子を実装し第2ノ領域にはスル
ーホール配線を施して回路を形成する第1の工程と、こ
の第1の工程によって形成された回路の電気特性?調整
又は検査する第2の工程と、第2の工程終了後に前記第
2の領域を第1の領域から分離除去する第3の工程と、
前記第2の領域を除去された第1の領域にクリップリー
ドを取り付ける第4の工程とから成る混成集積回路装置
の製造方法。 (2)絶縁基板における第1の領域と第2の領域との区
分を切り溝によって行なうことを特徴とする特許請求の
範囲第1項記載の混成集積回路装置の製造方法。 (3)絶縁基板の第2の領域に設けるスルーホール配線
を千鳥状に配列すること全特徴とする特許請求の範囲第
1項記載の混成集積回路装置の製造方法。
[Claims] (i) An insulating substrate is divided into a first region and a second region, conductive wiring is provided on the patterned surface of the insulating substrate, and an active element or a passive element is provided in the first region. The first step of mounting and forming a circuit by providing through-hole wiring in the second region, and the electrical characteristics of the circuit formed by this first step? a second step of adjusting or inspecting; a third step of separating and removing the second region from the first region after the second step;
and a fourth step of attaching a clip lead to the first region from which the second region has been removed. (2) The method for manufacturing a hybrid integrated circuit device according to claim 1, wherein the first region and the second region in the insulating substrate are separated by a cut groove. (3) The method for manufacturing a hybrid integrated circuit device according to claim 1, characterized in that the through-hole wiring provided in the second region of the insulating substrate is arranged in a staggered manner.
JP20175283A 1983-10-25 1983-10-25 Method of producing hybrid integrated circuit device Pending JPS6091696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20175283A JPS6091696A (en) 1983-10-25 1983-10-25 Method of producing hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20175283A JPS6091696A (en) 1983-10-25 1983-10-25 Method of producing hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6091696A true JPS6091696A (en) 1985-05-23

Family

ID=16446345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20175283A Pending JPS6091696A (en) 1983-10-25 1983-10-25 Method of producing hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6091696A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276254A (en) * 1987-05-08 1988-11-14 Nippon Abionikusu Kk Manufacture of hybrid ic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276254A (en) * 1987-05-08 1988-11-14 Nippon Abionikusu Kk Manufacture of hybrid ic

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