JPS6091673A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6091673A JPS6091673A JP19838383A JP19838383A JPS6091673A JP S6091673 A JPS6091673 A JP S6091673A JP 19838383 A JP19838383 A JP 19838383A JP 19838383 A JP19838383 A JP 19838383A JP S6091673 A JPS6091673 A JP S6091673A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- silicon
- layer
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 32
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 238000001312 dry etching Methods 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract 6
- 238000010438 heat treatment Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 64
- 239000010410 layer Substances 0.000 description 33
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000009528 severe injury Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野］
本発明は半導体装置の製造方法に関し、特にゲート絶縁
膜が窒化シリコンと酸化シリコンの少（とも２層から成
るＭＩＳ型半導体装置におけるゲート絶縁膜の加工に使
用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular a method for manufacturing a gate insulating film in an MIS type semiconductor device in which the gate insulating film is composed of at least two layers of silicon nitride and silicon oxide. It is used for processing.
し発明の技術的背景〕
ＭＯ８型半導体装置においてはゲート絶縁膜として熱酸
化膜すなわち酸化シリコン（Ｓｉ０２）膜が使用される
が、近時さらに誘（社）率の大きい窒化シリコン（５１
３Ｎ４ ）膜が使用されるようになっている。しかし窒
化シリコン膜単独ではリーク電流が存在し、特性を態化
させるため通常薄いシリコン酸化膜の上に窒化シリコン
膜を形成している。また、電極側から電子が流入してゲ
ートしきい値ｖｔｈを変動させることを防止するため、
また耐圧特性の向上のため、窒化シリコン膜の表面を酸
化して酸化シリコン膜を更に形成することも行われる。[Technical Background of the Invention] In MO8 type semiconductor devices, a thermal oxide film, that is, a silicon oxide (Si02) film is used as a gate insulating film, but recently silicon nitride (51
3N4) membranes are now being used. However, a silicon nitride film alone has a leakage current, and in order to improve the characteristics, a silicon nitride film is usually formed on a thin silicon oxide film. In addition, in order to prevent electrons from flowing in from the electrode side and changing the gate threshold value vth,
Further, in order to improve the breakdown voltage characteristics, the surface of the silicon nitride film is oxidized to further form a silicon oxide film.
これらの酸化シリコン膜、窒化シリコン膜は窒化シリコ
ンの高誘電率を生かすよう約１００χの比較的薄い膜厚
で形成される。These silicon oxide films and silicon nitride films are formed with a relatively thin film thickness of about 100x to take advantage of the high dielectric constant of silicon nitride.
第１図はこのような窒化シリコン膜をゲート絶縁膜とし
て有する半導体装置の製造方法を示す各工程ごとの断面
図であってシリコン基板１を約８００℃の雰囲気中で熱
酸化し熱酸化膜２を約１００Ｘの厚さで形成する。次に
減圧ＣＶＤ法により窒化シリコン膜（Ｓｉ３Ｎ４ ）
３を約１００Ｘの厚さで形成し、再び熱酸化を行って第
２の酸化膜４を形成する。次に多結晶シリコン層５をＣ
ＶＤ法で約４０００ Ｘの厚さに形成し、導体化するた
めにリンを拡散させ、さらにフォトレジスト１−６を形
成して露光し将来ゲートとなる領域に所定形状になるよ
うにパターニングを行えば第１図（ａ）の状態となる。FIG. 1 is a cross-sectional view of each process showing a method of manufacturing a semiconductor device having such a silicon nitride film as a gate insulating film, in which a silicon substrate 1 is thermally oxidized in an atmosphere of about 800° C. is formed to a thickness of about 100X. Next, a silicon nitride film (Si3N4) was formed using the low pressure CVD method.
3 is formed to a thickness of about 100X, and thermal oxidation is performed again to form a second oxide film 4. Next, the polycrystalline silicon layer 5 is
It is formed to a thickness of about 4000× by the VD method, phosphorus is diffused to make it conductive, and photoresist 1-6 is formed and exposed to pattern the area that will become the gate in the future into a predetermined shape. For example, the state is as shown in FIG. 1(a).
次にこのパターニングされたフォトレジスト層６をマス
クとして多結晶シリコン層５を等方性ドライエツチング
技術を用いてエツチングするとオーバーエツチングによ
り窒化シリコン膜３上の第２の酸化膜４も同時に除去さ
れ第１図（ｂ）に示す状態となる。すなわち、このとき
の多結晶シリコン層の幅Ｌ１はエツチング時に生じるサ
イドエツチングによりフォトレジスト層６０幅り。より
も小さくなっている。Next, using this patterned photoresist layer 6 as a mask, the polycrystalline silicon layer 5 is etched using an isotropic dry etching technique, and the second oxide film 4 on the silicon nitride film 3 is simultaneously removed due to overetching. The state shown in FIG. 1(b) is reached. That is, the width L1 of the polycrystalline silicon layer at this time is about the width of the photoresist layer 60 due to side etching that occurs during etching. It is smaller than.
次に電化シリコン膜３を等方性ドライエツチングを用い
てエツチングを行うと第１図（ｃｌの状態となる。この
エツチング時に等方性ドライエツチングを用いるのは、
リン酸セイル等のウェットエツチングではエツチングの
終点検出の確実性、薄膜に対する膜厚制御の容易性、量
産性等に関して問題があり、また反応性イオンエツチン
グ（ＲＩＥ：Ｒｓａｃｔｌｏｎ Ｉｏｎ Ｅｔｃｈｉｎ
ｇ ）では基板に与えるダメージが大キク、エツチング
量の均一性などに欠けるという問題がある一方で、等方
性ドライエツチングは基板へのダメージが少なくしかも
下地のシリコン熱酸化膜のエツチング量に対する窒化シ
リコン膜のエツチング量の比（選択比）を１０以上にと
ることができるためである。Next, when the electrified silicon film 3 is etched using isotropic dry etching, the state shown in FIG. 1 (cl) is obtained.
Wet etching such as phosphoric acid sail has problems with the reliability of etching end point detection, ease of controlling film thickness for thin films, mass production, etc., and reactive ion etching (RIE).
(g) has the problem of severe damage to the substrate and lack of uniformity in the amount of etching, while isotropic dry etching causes less damage to the substrate and the amount of nitriding compared to the amount of etching of the underlying silicon thermal oxide film. This is because the etching amount ratio (selectivity) of the silicon film can be set to 10 or more.
最後に不純物拡散によるソース、ドレイン領域７の形成
、層間絶縁膜８の形成、蒸着によるアルミニウム配＃９
の形成、ノぐツシベーション［１０の形成を公知の方法
で行うと第１図（ｄ）に示すＭＩＳ型半導体装置が得ら
れる。Finally, the source and drain regions 7 are formed by impurity diffusion, the interlayer insulating film 8 is formed, and the aluminum layer #9 is formed by vapor deposition.
When the formation of 10 and the formation of 10 are performed by a known method, the MIS type semiconductor device shown in FIG. 1(d) is obtained.
しかしながら、このような従来の方法では微細な半纏体
構造を実現することは困難である。However, it is difficult to realize a fine semi-woven structure using such conventional methods.
すなわち、窒化シリコン膜３のエツチング条件として通
常の窒化シリコンに対するエツチング条件を使用した場
合は酸化シリコンとの選択比が１〜３程度で小さいため
、ウェーッー内の位置によるエツチング量のばらつき、
ウェー７１間のエツチング喰のばらつきを考慮し１マー
ジンをもってエツチングを行うと下地の熱酸化膜やシリ
コン基板までエツチングされることになる。これを避け
るため窒化シリコンと酸化シリコンとの選択比を大きく
するようにガス条件を変えていくと多結晶シリコンに対
するエツチング条件に近似することになり、電化シリコ
ン膜４のエツチングを行うと同時に′電極となる多結晶
シリコン層５もエツチングされてその幅寸法はＬ２とな
る。例えば多結晶シリコン層５の厚さが４ｏｏｏ Ｘ
ｚ窒化シリコン膜３の厚さが９３′にであったとすると
フォトレジスト６０幅り。と多結晶シリコンｌＩ！５０
幅Ｌ２との差（Ｌｏ−Ｌ２）は約１．８μｍにもなり従
来のゲート絶縁膜がシリコン酸化膜のみである場合より
も約０．７μｍ大きくなる。このようなパターン変換誤
差は窒化シリコン膜３上の酸化シリコン膜４の厚さが増
加すると更に拡大し、微細な半導体構造を得ることが困
難であるという問題がある。In other words, when normal etching conditions for silicon nitride are used as the etching conditions for the silicon nitride film 3, the etching selectivity with respect to silicon oxide is small at about 1 to 3, so the etching amount varies depending on the position within the wafer.
If etching is performed with one margin in consideration of variations in etching depth between wafers 71, the underlying thermal oxide film and silicon substrate will also be etched. To avoid this, if the gas conditions are changed to increase the selectivity between silicon nitride and silicon oxide, the etching conditions will approximate those for polycrystalline silicon. The polycrystalline silicon layer 5 is also etched, and its width becomes L2. For example, the thickness of the polycrystalline silicon layer 5 is 4ooo
zIf the thickness of the silicon nitride film 3 is 93', it is about the width of the photoresist 60. and polycrystalline silicon II! 50
The difference from the width L2 (Lo-L2) is about 1.8 μm, which is about 0.7 μm larger than when the conventional gate insulating film is only a silicon oxide film. Such pattern conversion errors further increase as the thickness of the silicon oxide film 4 on the silicon nitride film 3 increases, posing a problem in that it is difficult to obtain a fine semiconductor structure.
本発明はこのような問題を解決しようとし℃なされたも
ので、多結晶シリコン電極に対するノぐターン変換差の
小ないゲート絶縁膜加工を可能にする半導体装置の製造
方法を提供することを目的とする。The present invention was developed in an attempt to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables processing of a gate insulating film with a small difference in turn conversion with respect to a polycrystalline silicon electrode. do.
〔発明の概要〕
上記目的達成のため、本発明においては多結晶シリコン
層のエツチング後、この多結晶シリコン層を酸化してそ
の表面に窒化シリコン膜上の酸化シリコン膜よりも厚い
酸化シリコン膜を形成し、次いで窒化シリコン膜をエツ
チングするようにしておす、窒化シリコン膜のエツチン
グの際に多結晶シリコン層のエツチングが進んでこの多
結晶シリコン層のパターン変換誤差が大きくなることを
防止できるものである。[Summary of the Invention] In order to achieve the above object, in the present invention, after etching a polycrystalline silicon layer, the polycrystalline silicon layer is oxidized to form a silicon oxide film on its surface that is thicker than the silicon oxide film on the silicon nitride film. It is possible to prevent etching of the polycrystalline silicon layer from progressing during etching of the silicon nitride film and pattern conversion error of the polycrystalline silicon layer from increasing. be.
以下、第２図を参照しながら本発明にかかるゲート絶縁
膜の加工方法を詳細に説明する。Hereinafter, a method for processing a gate insulating film according to the present invention will be explained in detail with reference to FIG.
第２図は本発明の一実施例を示す各工程の断面。FIG. 2 is a cross section of each process showing an embodiment of the present invention.
図であって、まず従来例と同様にシリコン基板２１を８
００℃の雰囲気中で熱酸化して熱酸化膜ｎを約１００Ｘ
の厚さで形成し、窒化シリコン膜ｎを減圧ＣＶＤ法によ
り約１００＾の厚さで形成する。次に再び熱酸化を行っ
て第２の酸化層別を３０＾ないし５０Ｘの厚さで形成し
、その上に多結晶シリコン層２５をＣＶＤ法で約４００
０ Ｘ の厚さで形成しリン拡散を行って導体化する。In this figure, first, as in the conventional example, a silicon substrate 21 is
Thermal oxidation is performed in an atmosphere of 00℃ to form a thermal oxide film n of approximately 100X.
A silicon nitride film n is formed to a thickness of about 100^ by low pressure CVD. Next, thermal oxidation is performed again to form a second oxide layer with a thickness of 30~50X, and a polycrystalline silicon layer 25 is deposited on top of it with a thickness of about 40X by CVD.
It is formed to a thickness of 0.times.0.times., and is made into a conductor by performing phosphorus diffusion.
フオトレジス）１ｍ２６を形成して所定の領域に所定の
パターンで露光を行えば第２図（、）に示すようなパタ
ーニングされたフォトレジスト層かが得られる。By forming a photoresist layer of 1 m26 and exposing a predetermined area in a predetermined pattern, a patterned photoresist layer as shown in FIG. 2(,) can be obtained.
次にこのノｅターニングされたフォトレジスト層九をマ
スクとして等方性ドライエツチング法により多結晶シリ
コン層５をエツチングすると多結晶シリコン層５０幅は
フォトレジスト寸法Ｌ１ｏよりも約１μｍ小さいり、１
となる。なおこのエツチング時に窒化シリコン膜お上の
酸化膜讃は通常オーバーエツチングにより除去されるの
で第２図（ｂ）に示す状態が得られる。Next, when the polycrystalline silicon layer 5 is etched by an isotropic dry etching method using the photoresist layer 9 that has been turned as a mask, the width of the polycrystalline silicon layer 50 is approximately 1 μm smaller than the photoresist dimension L1o.
becomes. Note that during this etching, the oxide film on the silicon nitride film is usually removed by over-etching, so that the state shown in FIG. 2(b) is obtained.
次に７オトレジスト層拠を除去し、酸素雰囲気中に水素
を混入させ８５０℃の温度で燃焼させるＢＯＸ （Ｂｕ
ｒｎｉｎｇ ０ｘｉｄａｔｉｏｎ ：燃焼酸化）法を用
いて多結晶シリコン層５を酸化させると１２００〜１３
００Ｘの厚さの酸化膜ごが形成される。このとき、窒化
シリコン膜おも同時に酸化されるが、多結晶シリコン層
５よりもはるかに酸化の進行が遅いために窒化シリコン
膜お上には３０Ｘ以下の薄い酸化膜が形成されるのみで
ある。Next, the BOX (Bu
When the polycrystalline silicon layer 5 is oxidized using the rning oxidation (combustion oxidation) method, it becomes 1200 to 13
An oxide film having a thickness of 00X is formed. At this time, the silicon nitride film is also oxidized at the same time, but since the oxidation progresses much more slowly than the polycrystalline silicon layer 5, only a thin oxide film of 30X or less is formed on the silicon nitride film. .
次に窒化シリコン換器を等方性ドライエツチングまたは
反応性イオンエツチング（ＲＩＥエツチング）によりエ
ツチングで除去する。このエツチング条件として酸化シ
リコンに対する窒化シリコンのエツチングの選択比が大
きい多結晶シリコンに対するエツチング条件に近い条件
を選択すると、多結晶シリコン層５は厚い酸化膜に覆わ
れているためにエツチングが進まない一方で、窒化シリ
コン換器は除去されて第２図（ｄ）の状態が得られる。The silicon nitride film is then etched away using isotropic dry etching or reactive ion etching (RIE etching). If etching conditions are selected that are close to the etching conditions for polycrystalline silicon, in which the etching selectivity of silicon nitride to silicon oxide is high, etching will not proceed because the polycrystalline silicon layer 5 is covered with a thick oxide film. Then, the silicon nitride converter is removed to obtain the state shown in FIG. 2(d).
このときの多結晶シリコン層５０幅もまし、１のままで
ある。The width of the polycrystalline silicon layer 50 at this time also remains 1.
最後に素子分離を行うフィールド酸化膜あの形成、不純
物拡散によるソース・ドレイン領域四の形成、層間絶縁
膜３ｔ、ｌＵ）形成、蒸着法によるアルミニウム配線３
１の形成、ノξツシペーション膜３２の形成等を公知の
方法で行うと第２図ｔｅ＋に示すＭＩＳ型半導体装置が
児成する。Finally, the field oxide film for element isolation is formed, the source/drain regions 4 are formed by impurity diffusion, the interlayer insulating film 3t, lU) is formed, and the aluminum wiring 3 is formed by vapor deposition.
By performing the formation of 1, the formation of the insulation film 32, etc. by known methods, an MIS type semiconductor device shown in FIG. 2te+ is formed.
以上の実施例においては、多結晶シリコン層の酸化にＢ
ＯＸ法を用いているが、多結晶シリコン層に厚い酸化膜
が、窒化シリコンｊ−に薄い酸化膜がそれぞれ形成され
るのであれば方法や温度、雰囲気、時間等の条件如何を
問うものではない。In the above embodiment, B is used for oxidizing the polycrystalline silicon layer.
Although the OX method is used, as long as a thick oxide film is formed on the polycrystalline silicon layer and a thin oxide film is formed on the silicon nitride layer, the conditions such as method, temperature, atmosphere, time, etc. do not matter. .
また実施例においては多結晶シリコン層は窒化シリコン
膜の上部に形成された酸化膜の上に形成されているが、
この酸化膜が存在しない場合も同様に本発明を適用でき
る。Furthermore, in the embodiment, the polycrystalline silicon layer is formed on the oxide film formed on the silicon nitride film, but
The present invention can be similarly applied even when this oxide film does not exist.
さらに本発明はＭＩＳ型のトランジスタのみでなく、Ｍ
ＩＳ型のキャパシタにも同様に適用できるものである。Furthermore, the present invention applies not only to MIS type transistors but also to M
It can be similarly applied to IS type capacitors.
以上のような本発明によれば窒化シリコン膜をゲート絶
縁膜の一部とし、この上に形成された多結晶シリコン層
をゲート電極とする半導体装置の製造方法において、多
結晶シリコン層をパターニングした後、この多結晶シリ
コン層に窒化シリコン膜上の酸化シリコン膜よりも厚い
酸化シリコン膜を形成し、この厚い酸化シリコン膜をエ
ツチングにより除去するようにしているため、窒化シリ
コン膜のエツチングの際に厚い酸化シリコン膜の存在に
より多結晶シリコン層のエツチングが進行することはな
く、パターン変換差が小さくなるため微細なＭＩＳ型半
導体構造を得ることができる。According to the present invention as described above, in a method for manufacturing a semiconductor device in which a silicon nitride film is used as a part of a gate insulating film and a polycrystalline silicon layer formed thereon is used as a gate electrode, the polycrystalline silicon layer is patterned. Afterwards, a silicon oxide film that is thicker than the silicon oxide film on the silicon nitride film is formed on this polycrystalline silicon layer, and this thick silicon oxide film is removed by etching. Due to the presence of the thick silicon oxide film, etching of the polycrystalline silicon layer does not progress, and the difference in pattern conversion becomes small, making it possible to obtain a fine MIS type semiconductor structure.
第１図は従来のＭＩＳ型半導体装置の製造方法を示す工
程断面図、第２図は本発明にかかるＭＩＳ型半導体製造
装置の製造方法を示す工程断面図である。
ｌ、２１・・・シリコン＆［，２，２２，４，２４・・
・シリコン酸化膜、３．２３・・・窒化シリコン膜、５
，２５・・・多結晶シリコン層、６．２６・・・フォト
レジスト、２７・・・シリコン酸化膜。
出願人代理人 猪 股 清
第１図
（ａ）
（ｂ）
（ｄ）
第２図FIG. 1 is a process sectional view showing a conventional method for manufacturing an MIS type semiconductor device, and FIG. 2 is a process sectional view showing a method for manufacturing an MIS type semiconductor device according to the present invention. l, 21... Silicon & [, 2, 22, 4, 24...
・Silicon oxide film, 3.23...Silicon nitride film, 5
, 25... Polycrystalline silicon layer, 6.26... Photoresist, 27... Silicon oxide film. Applicant's agent Kiyoshi Inomata Figure 1 (a) (b) (d) Figure 2
Claims (1)
ト絶縁膜とし、このゲート絶縁膜の上に形成された多結
晶シリコン層をゲート電極とする半導体装置の製造方法
において、 前記多結晶シリコン層をエツチングにより所定形状に・
ぞターニングする工程と、 前記パターニングされた多結晶シリコン層に前記窒化シ
リコン膜上に形成された酸化シリコン膜よりも厚い酸化
シリコン膜を形成する工程と、この多結晶シリコン層に
形成された前記酸化シリコン膜をマスクとし℃前記窒化
シリコン膜をエツチングにより除去する工程、 とを有することを特徴とする半導体装置の製造方法。[Claims] A method for manufacturing a semiconductor device in which at least two layers of a silicon oxide film and a silicon nitride film are used as a gate insulating film, and a polycrystalline silicon layer formed on the gate insulating film is used as a gate electrode, The polycrystalline silicon layer is etched into a predetermined shape.
a step of forming a silicon oxide film thicker than a silicon oxide film formed on the silicon nitride film on the patterned polycrystalline silicon layer; 1. A method of manufacturing a semiconductor device, comprising: using a silicon film as a mask, removing the silicon nitride film by etching at °C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19838383A JPS6091673A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19838383A JPS6091673A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6091673A true JPS6091673A (en) | 1985-05-23 |
Family
ID=16390207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19838383A Pending JPS6091673A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6091673A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54155782A (en) * | 1978-05-26 | 1979-12-08 | Rockwell International Corp | Method of fabricating semiconductor |
-
1983
- 1983-10-25 JP JP19838383A patent/JPS6091673A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54155782A (en) * | 1978-05-26 | 1979-12-08 | Rockwell International Corp | Method of fabricating semiconductor |
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