JPS6091472A - Microprocessor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in the implementation of microprocessor integrated circuit designs. The present microprocessor integrated circuit design is directed, in part, to a circuit configuration that provides improved microprocessor performance and functionality. The invention further relates in part to improved integrated circuit structures and topologies. More particularly, the present invention relates to an improved data path multiplexing arrangement and bus operating configuration. The present invention further relates to a special ground balance configuration that improves integrated circuit performance. The present invention is a further improved register file storage circuit. The invention further relates to improved timing circuits for microprocessor integrated circuits and related applications. The present invention relates to a further improved read only memory (ROM) circuit.

A wide variety of integrated circuit microprocessors are known in the art. All major semiconductor manufacturers in the United States
0 MO8 configuration or bipolar integrated circuit configuration with integrated injection logic (I2L) or I2
The company sells microprocessor integrated circuits formed in transistor-to-transistor logic (TTL) configurations.

For example, the F9445 microprocessor integrated circuit available from Fairchild Camera and Instrument Corporation is a high performance combined I2L and TTL integrated circuit. A more detailed description of the integrated circuit is provided in the following US patent applications: US Pat.

U.S. Patent Application No. 167.614, Inventor Ilamra
J K, IIingarh, “Coupled Integral Injection Logic
Transistor Transistor Logic Microprocessor Integrated Circuit Design (COMBINED INTEGRATED
INJECTION MICROPROCESSORI
NTEGRATED CIRCUIT DESIGN)
J, filed on July 11, 1980.

U.S. Patent Application No. 167.607, Inventor: Michael
lG.

Mldadejovsky, “Cycle Counter for Microprocessor Integrated Circuits”
FORl MICROPROCESSORINTEGR
ATED CIRCUIT) J, filed on July 11, 1980.

Although the art of microprocessor integrated circuit design is fairly well established, there is a need for further improvements in microprocessor integrated circuit design to obtain higher levels of functionality and performance in high performance microprocessors.

SUMMARY OF THE INVENTION The present invention has been developed in view of the above points, and it is an object of the present invention to provide an improved data path multiplexing operation and bus operation configuration. Another object of the present invention is to provide an I2L integrated circuit with reduced injection bus width and proper bias conditions throughout the circuit. Yet another object of the present invention is to provide an improved register file cell configuration for a microprocessor integrated circuit. It is a further object of the invention to provide an improved timing circuit for a register file cell according to the invention. Yet another object of the present invention is to provide a ROM structure that allows efficient layout of ROM within a microprocessor integrated circuit. Yet another object of the present invention is to provide a ROM that allows quick access to microcode stored within the ROM.
It is to provide configuration.

A microprocessor integrated circuit according to the present invention has a register file comprising a first plurality of registers. Each of the first plurality of registers is connected to one of a second plurality of local buses. These local buses are connected to the main bus by multiplexing means.

According to another feature of the invention, the microprocessor integrated circuit has a main injector bus and a ground return bus in the data path. At least one branch ground bus is provided. A ground balance resistor connects the ground return bus and the branch ground bus.

According to yet another feature of the invention, the memory storage circuit has a latch with a pair of outputs.

A data input and an enable signal input to the latch are provided to control data input to the latch. The storage circuit has a pair of output enable signal inputs, each connected to control one of the pair of outputs.

According to yet another feature of the invention, the timing circuit includes delay means connected to receive input timing pulses generated in response to a plurality of inputs. The output of the delay means is connected to provide a delayed timing pulse to the output gate. The output gate is also connected to receive an input timing pulse. The output of the output gate is used, for example, by the latch memory cell of the present invention as a latch enable timing circuit.

According to yet another feature of the invention, the D-type flip-flop circuit used in the microprocessor integrated circuit of the invention has a master section and a slave section.

The input of data from the D input to the master section is controlled by the clock input.

The input and preset inputs, independent of the clock input, function to set the desired state of the flip-flop 17 for a pair of outputs from the flip-flop from any previous state.

According to a further feature of the invention, the microprocessor integrated circuit has a ROM with a first plurality of X and Y addressable memory locations arranged in words, bits and pages. are doing. The X direction addresses one of the second plurality of words on each page. The Y direction is one of the third plurality of pages and one of the fourth plurality of pages 1 to 1 of the fourth plurality.
Address one.

According to yet another feature of the invention, a decode circuit particularly adapted for use with ROM includes a plurality of multiple emitter page select transistors. One of the multiple emitters of each page select transistor is connected to provide an output from the decode circuit. Another one of the multiple emitters of each page select transistor is connected to the base of that transistor and receives a reference potential.

By providing these features in a microprocessor integrated circuit, it is possible to improve the performance of the circuit. Although it is possible to provide improved performance by any one or a combination of several of these features of the invention,
One embodiment of the invention incorporates all of these features into a single microprocessor integrated circuit.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B illustrate a microprocessor integrated circuit 50 in accordance with the present invention. This microprocessor 50 consists of five main parts, namely a data processor 52, a microprogram control 5
4, an address processor 56, an interlaced fault processor 5'8, and a timing unit 60.

A 16-bit wide data processor section 52 is responsible for all data processing within microprocessor 50.

Data processor 52 has functional blocks described below. 17-bit arithmetic logic unit (ALU) 6
2 receives input from the A input bus 66 at 64 and also receives input from the B input bus 68 via a preshifter and mask 69.
Receives input from input bus 0. The output from ALU 62 is provided to ALU bus 74 at 72 and
6 via the shifter and mask 78 to the shifter bus 8
0. Register file 82 includes 16 general purpose registers R11-R15 and 6 working registers. The register file 82 is connected to the ALU at 84.
It receives inputs from bus 74 and provides inputs to A input bus 66 and B input bus 0 at 86 and 88, respectively.

Memory data register 90 receives input from multiplexer 92 at 94 and provides inputs to A input bus 66 and B input bus 0 at 96 and 98, respectively. Multiplexer 92 connects ALU bus 74 at 100
and receives input from information bus 1 at 104.
Receives input from 02. The multiplexer 92 is also 1
At 06, input is provided to the instruction register 108 in the microprogram control unit 54. Instruction register 108 provides input to six input bus 66 at 110. Two timers 112 and 114 receive input from shifter bus 80 at 116 and input from A at 118.
Provides input to input bus 66 . Constant ROM120 is 1
RO from ROM address register 122 at 24
Receive M address. ROM address register 122
receives input from shifter bus 80 at 126 .

The status register 130 registers the ALU 62 at 132.
and from the shifter bus 80 at 134 . This status register 130 provides an input to the six-input bus 66 at 136 .

Instruction register 108 in microprogram control unit 54
provides the new instruction fetched into instruction register 108 to mapping PLA 150 at 152 .

Multiplexer 156 provides input at 160 to microcontrol store 162, which contains execution routines and effective address routines. Micro control store 16
2 at 166 microprogram register 164
21- generates three output fields to. The next address field provided to microprogram register 1d4 is provided at 168 to multiplexer 156.

Multiplexer 156 also provides an input to incrementer 172 at 170 . Incrementer 172 is 17
6 provides an input to the next address register 174. Next address register 174 provides an input to multiplexer 156 at 178 . Microprogram register 164 provides the branch field output from microcontrol store 162 to branch PLA 180 at 182 . Branch P LA 180 provides an input to multiplexer 156 at 183. Branch condition is 184
Branch PLA 18 by data processor section 52 at
0.

A third output field from microcontrol store 162 provided via microprogram registers 164 controls the operation of all components within data processor 52 and is provided to data processor section 52 at 186 .

−? ? - Address processor 56 has an instruction counter (IC) 200, which receives input at 202 from ALU bus 74. I C2'00 is A at 204
Provides an instruction address to input bus 66. IC 200 also provides the instruction address to information bus multiplexer 206 at 208 and to incrementer 210 at 212. The output from incrementer 210 is provided to IC 200 at 214 and to memory address register (MAR) 216 at 218.

Additional inputs to MAR 216 are provided by information bus 102 at 220 and by ALU bus 74 at 222. MAR 216 determines the addresses for all operands and provides address outputs at 224 to incrementer 210 and to information bus multiplexer 206. Additional input to the information bus multiplexer is provided by ALU bus 74 at 226.

The output of information bus multiplexer 206 is provided to information bus 102 at 228. Incrementer 210 provides IC and operand address update parallel operations for data processor section 52.

Whether generated internally or externally to microprocessor 50,
Fault processor section 58 handles all interrupts and faults. To Interlab 1 - Fault processor 58 has a bending (pending) interconnected register (PNP) 250 . Fault register logic (FT) 252 provides input to PIR 250 at 254 . Fault input is 25
6 to the FT 252 and from the shifter bus 80 at 258. The output from FT 252 is also provided at 260 to A input bus 66. Additional interwoven inputs to PIR 250 are provided at 262 and from shifter bus 80 at 264. The output from PIR 250 is provided at 266 to mask interleaved enable logic 268 . Mask register (MK) 270 provides an input to mask interleaved enable logic 268 at 272 . MK2
Input to 70 is provided at 274 from shifter bus 80. Mask interleaved enable logic 268 provides an output at 276 to priority encoder 278 .

Priority encoder 278 provides an output to latch 282 at 280 . Latch 282 provides an output to A input bus 66 at 284 .

Timing unit 60 generates internal and external strobes necessary for internal operations of microprocessor 50 and different bus operations. Internal inputs are provided at 292 to and from timing arbitration unit 290 . The external inputs of the microprocessor 50 are 2
At 94, the timing arbitration unit 2
90 and from there.

As shown in the state diagram of FIG.
The basic machine cycle for a computer has 3.25-4 or 5 CPU clock cycles or states. The symbols shown in FIG. 2 have the following meanings.

A = asserted (active) NA = not 1 - asserted ALBR = ALU branch cycle (5 states) - internal signal ABRT = abort condition - internal signal BUSREQ = bus request BUSGNT = bus permission input BUSLOCK = bus RDYA=RDYA input RDYD=RDYD input Sz=high impedance state -C, PU driver is 3-
situation.

Condition S. , S4. The 3-state cycle consisting of S is used for operations completely internal to ALU 62. Condition S. , S□+S21 S3 is used for minimum length operations using one of the buses. Condition S. = s,, s2. s3.5aA=9
g - or S. , s4. 5SI S A consisting of s s s
tsA - state cycle microprogram control store 16
This applies to operations that use the results of the current operation of ALU 62 to determine the next address in ALU 62. This 5
- State cycles also apply to operations following an abort condition. All timing cycles are in state S. In that state, timing unit 60 receives the necessary control information to initiate a bus cycle or an internal ALU cycle.

It is possible to extend the bus cycle by manipulating the BUSGNT, RDYA or RDYD external inputs. These signals are routed to bus 102 as shown in FIG.
The microprocessor 50 is maintained in a high impedance state SZ when the microprocessor 50 is assigned to another microprocessor 50 or a direct memory access (DMA) device, an address phase in state S1 or a data phase in state S3, respectively.

FIG. 3 shows external inputs to and from microprocessor 50. Clock power 300 to microprocessor 50 is 0-20M1lzCPU in 302
CLK signal and a 100kHz timer CLK signal at 304. The external request 306 is
The R E S E T signal initializes the microprocessor 50 to a low active state at 308 and the C0N
REQ signal, the latter signal initializing console operation to a low active state after microprocessor 50 executes the current instruction.

A total of nine interconnected forces 310 are supplied to the microprocessor 50. The PWRDN INT signal 312 for power-down interconnected is set according to the interconnected mill mode pit in the configuration register.
It becomes active at its front end or at a high level. 314
The USR6INT through USR5INT signals are user-interconnected and are active at the positive end or at a high level, depending on the interwoven mode bit in the configuration register. IOL in 316
Y INT and l0L2 The INT signal is an input/output level interrupt and is a high active input that can be used to expand the number of user interrupts.

Fall 1 - Human power is microprocessor 5 in 318
0. The MEMPRT ER signal at 320 represents a memory protect error and is a low active input generated by an external memory management unit (MMU) and/or an external block protect unit (BPU).

It is activated by the BUS BUSY signal, which will be described later.
Sampled in bit 0 of fault register 252 in a U bus cycle or in pins 1-1 if it is not a CPU bus cycle. MEM PARER in 322
Double signal indicates memory parity error, and BUS
Low active input sampled into bit 2 of fault register 252 by the BUSY signal. EX
TADRER signal 324 represents an external address error;
BUS - Low active input sampled into bit 5 or bit 8 of fault register 252 by the BUSY signal. 5YSFLTo in 326
The 5YSFLT□ signal represents a system fault and is active at the front edge, bit 7 or bit 13.
and 14 are set in the fault register 252, respectively.

The IBo to B15 information bus input and output signals at H.328 represent active bidirectional time multiplexed address and data information on the 16-bit information bus 102.

Bus 102 is in three states during bus cycles that are not assigned to microprocessor 50. The IB2 signal is the most significant bit.

The status bus output from the microprocessor 50 is 33.
Supplied at 0. AKO to AK in 332
3 address key signal is external MMU for memory access
is a high active output used to match the access lock within the Inconsistency is one of several possible states
MEM P in 320 by MMU
Forces the RT E- signal to its low active state. 3
The ASO to AS3 address status signal in the 3490- is a high active output that selects a page register group in the external MMU.

An error output is provided at 336. The non-restartable error signal UNRCVER at 338 is a high active output indicating the occurrence of an error that is classified as non-restartable. The instruction in which this error occurs is aborted. 34
The major error signal MAJ ER at 0 is a high active output and represents the occurrence of an error classified as major.

The instruction in which this error occurred is also aborted.

There are 34 discrete outputs from the microprocessor 50.
2. The direct memory access enable signal DMA_ER at 344 is active high, indicating that DMA is enabled. DMA when external request signal RESE is active
is disabled. NML PW in 346
The RUP signal is high active and the microprocessor 5
0 indicates successful completion of the built-in tests in the initialization sequence. The new start signal 5NEW at 348 is active high, indicating that a new instruction will start execution in the next cycle. This information is useful for instruction tracing. 35
1 at 0 to reset signal TRIGOR8
T is the low active discrete output.

Bus control inputs and outputs to and from microprocessor 50 are provided at 352.

The read/write output signal R/W at 354 represents the direction of data flow. A high signal represents a read or input operation, and a low signal represents a write or output operation. The output at 354 is tristate during bus cycles not assigned to microprocessor 50. M in 356
The /IO memory or I10 output signal indicates whether the current bus cycle is memory (high) or I10 operation (low). Output 356 is tristate during bus cycles not assigned to microprocessor 50. 35
The D/I data to command output 31- signal at 8 indicates that the current bus cycle access is for data when high, while for an instruction when low. Output 358 is the microprocessor 5
It is in 3 states during bus cycles that are not assigned to 0. Address strobe signal 5TRBA in 360
is used to latch the memory or XIO address to the high active output in an external latch on the strobe high to low transition. The output 360 is.

There are three states during bus cycles that are not assigned to microprocessor 50. Address ready signal RDYA
is a high active input used to extend the address phase of the bus cycle. Data strobe signal 5TRBD in H.364
is a low active output used to strobe data within the memory and XIO cycles. The output at 364 is tristate during bus cycles not assigned to microprocessor 50. The data ready signal RDYD at 366 is a high active input used to extend the data phase of the bus 33-32- cycle. To accommodate slower memory devices, wait states are inserted unless RDYD is active.

Bus arbitration inputs and outputs are provided at 370 to and from microprocessor 50. 37
The output signal BUSREQ at 2 is a low active output, indicating that microprocessor 50 is requesting the bus. This signal becomes inactive when microprocessor 50 acquires the bus and begins a bus cycle. BUSGN supplied to 374 from external arbiter
The T signal is a low active input and the microprocessor 5
0 indicates that there is currently a priority bus request. If the bus is not locked, microprocessor 50 initiates a bus cycle with the start of the next CPU clock. BUS BUSY in 376
The signal is a low active bidirectional signal used to establish the beginning and end of a bus cycle. The trailing low to high transition is used to sample the bit into fault register 252. This signal is tristate on bus cycles not assigned to microprocessor 50. However, microprocessor 50 uses BtJS to latch bus cycle faults other than microprocessor 50 into fault register 252.
Monitor BUSY line 376. BUS in 378
The LOCK signal is a low active, bidirectional signal used to lock the bus for subsequent bus cycles. During unlocked bus cycles, BUS
LOCK imitates BUS BUSY.

During bus cycles not assigned to microprocessor 50, BUS LOCK is in three states.

The microprocessor wiring 380 is grounded. Wire 382 provides a 225 mA ■ CC input to microprocessor 50 at a nominal +5 ■. Wiring 384 is nominally +1.
3V and 1.4A voltage vINJ1 and vINJ2 are supplied to the microprocessor 50.

FIG. 4 shows ROM 4.0 for implementing the microcontrol store 162 used in the present invention. FIG. 2 is a block diagram of OO. Address portion 402 contains column addresses within memory portion 404, which are page and pill-oriented as shown at 406. This ROM is row addressed at 410. In the X direction, one of the 200 words in each page is addressed, and in the Y
addresses one of four pages.

FIG. 5 shows ROM4. A decode circuit 450 is shown that is used to access OO. For speed considerations, it is desirable to limit the voltage on node C. Therefore, node A is set to 4Vbe and node B is set to 3Vbe. The l-transistor Q1 charges the high base capacitance node and discharges the diode Q3. 1-transistor QAI, QA2°QA3. QA4 is 1 of 4 pages
This is for selecting one. In the preferred embodiment of the circuit, Vcc is 4Vbe at node A with a minimum of 4.5V at startup.

-35= FIG. 6 shows a reference circuit 500 used with ROM 400 of FIG. This reference circuit reduces the R
OM4. Important for OO speed. Additionally, the reference circuit 500 limits the custom resistance within each xi required for different loads depending on how many emitter contacts are connected to each x-ray in the ROM. To contribute. Only a constant resistor is needed for each of the 200X addresses, and the ROM400
The layout time has been reduced. The base 502 of the transistor QBI conducts only a very small current, and Ioj is basically ■.

is equal to

FIG. 7 shows reference circuit 520 connected to node B (FIG. 5). Emitter 522 is set to 3Vbe. Since the current conditions required for the microprocessor integrated circuit 50 are high, that is, the total current Ij, nj is approximately 1.4.
A, it is important to carefully control the voltage drop on each of the injection and ground buses 602, 604. In order to maintain proper bias conditions for all parts of integrated circuit 50,
A maximum voltage differential of 25 mV must be maintained on all 2L transistors VBIE over the operating temperature range of integrated circuit 50.

Figures 8 and 9 show details of the I2L power within the present microprocessor integrated circuit. For injection bus 602, the voltage drop across bus 602 is reduced by drop resistor 60.
6 (FIG. 8). descending resistance 60
The value of 6 determines the current in injection branch 608, which is set by the number of I2L transistors connected to that branch. For ground bus 604, the width of ground bus 604 is typically increased to reduce the ohmic voltage drop and approach a perfect ground condition, ie, zero pol 1- everywhere. However, to achieve this result, the dimensions of bus 604 would be significantly larger due to the higher current.

According to the present invention, ground balance is performed to eliminate such restrictions. Instead of trying to reduce the ground voltage to zero, the actual ground voltage is connected to the ground balance resistor 610.
The reference voltage value VGref is increased through the reference voltage VGref. Therefore, the voltage drop across main ground bus 604 is accounted for in the value of resistor 610.

To minimize the total power dissipation of chip 50, VGre
It is necessary to keep f as small as possible. VGer
The value of f is essentially the maximum voltage drop V across the main ground bus 604 and the maximum voltage drop V across the ground balance resistor closest to the points GMAX and VGMAX.
GR.

On the other hand, the value of VGR is determined by the ground current Ig and the minimum obtained resistance value Rmin.

FIG. 10 illustrates a register file data path bus configuration 600 that forms part of the present invention.

The bus operation configuration shown in FIG.
This has been implemented for the data path within.

This bus operational configuration reflects a two-level addressing configuration, ie, having a primary address and a local address. The primary address is e.g. register file, IR
, MDR, IC, MAR, etc. are determined. In the register file, the local address determines the particular register being selected. The addressing configuration is the same for the two inputs to the ALU (A and B buses). Only the operation of one of these buses will be described.

A 5-bit address (one of 32) is required to address register file 82, with 5 bits required for the A address and 5 bits for the B address. 2 each having up to 16 registers 622
The two pages are addressed in parallel using 4-bit addresses (1 of 16). Each page is connected to a separate local bus 624. To select or multiplex one of the two local buses 624 for the main bus 626, a fifth address pin l~ is coupled with the register file 82 main address selection signal.

Fundamentally, the bus operating configuration reduces the total propagation delay. In a simple bus configuration, all registers may be connected to a single local bus. In that case, the local bus has a total load capacitance of up to 32 collectors in addition to the wiring capacitance. Instead, two local buses 62
By using an arrangement with 4, the capacity of each local bus is reduced by half. As a result, approximately 8 nanoseconds is reduced in local bus access time. The simplified address decoder (one of 16 instead of one of 32) reduces the propagation delay in the ALU cycle by one additional gate delay. Therefore, the addressing configuration described above reduces the propagation delay in an ALU cycle by about 12 nanoseconds.

Several additional advantages in chip layout are obtained by using the present bus operating configuration. Each register has three control signals: one clock signal (WRI
TE) and two output enable signals (READ) for the dual boat register. By using this two-local bus configuration, it is possible for two registers to share the same READ signal, but not for the WRITE signal, thus reducing the number of control signals. It has been reduced by 1/3. It is particularly important in chip layout because the number of control signals determines the width of the data path. The chip area savings thereby significantly offset the area increase due to the additional local bus per bit.

FIG. 11 shows an improved latch dual port random access memory (RAM) circuit 900 used within register file 82 of microprocessor integrated circuit 50. In place of the D-type flip-flop typically used for this purpose, circuit 900 offers a number of advantages. A dual port D flip-flop requires 12 gates in practice, but circuit 900 only requires 10 gates. The importance of reducing the number of gates in the microprocessor integrated circuit 50 of the present invention is that
This is indicated by the fact that 25% of the gates are in the register file. Saving two gates in each cell in the register file results in a 15% reduction in input power to each cell and a 10% reduction in cell area.

When implementing register file cells with latches, it was necessary to solve timing problems and problems related to glitches in the latch output signals. Timing issues arise from the fact that the data input to the register file is shared by other registers on a common input data bus. These other registers are implemented in D-type flip-flop form, and they are edge triggered. It is therefore necessary to generate a special latch enable signal EN from the main clock pulse used to edge trigger the D flip-flops of these other registers. The pulse width of the EN signal is
Adjustments are made so that only data inputs appropriate within 00 are latched. As mentioned above, the EN signal is
7 is generated from the circuit shown in FIG.

A correction function was also required to avoid glitches in the latch output signals QA and QB following the leading edge of the EN signal. After the data is latched into the register file, the output enable signal in the later part of the cycle is used to reach the register file from the register file output bus.
- No glitches appear.

The dual boat latch cell 900 shown in FIG. 924. Furthermore,
Output enable buffer 92 consisting of gate 9 and]O
6 is also provided. If desired, output game 1-92
/1 can be connected to gates 1-5 to change the polarity of the output signals QA and QT3.

To explain the operation, when the latch enable signal 43-EN is asserted (low active), the latch 92
0 becomes transparent and input data D is latched onto gates 4 and 5. Latch output 924 remains open circuit unless output enable signals OEA and OEB are asserted; therefore, latch enable signal EN can be deasserted and latch 924
20 becomes opaque. Output enable signals EA and OEB can be asserted (active low) at any time, and the data latched on gates 4 and 5 are transferred to the QA and QB outputs independently of each other. During a WRITE operation, a glitch may appear at the output of gate 4. If it is possible to delay the READ operation from the WRITE operation by more than two gate delays, the glitch will not appear on the QA and QB outputs.

FIG. 12 shows a D-type flip-flop circuit 700 with asynchronous clear and preset in accordance with the present invention. FIG. 13 is a truth table for circuit 700. 14-16 are waveform diagrams useful in understanding the operation of circuit 45-44-700.

Flip-flop 700 has a master section 702 and a slave section 704. The outputs of master section 702 are at nodes A and B.

The inputs of the slave section are at nodes A, B, C, and D. The CLK clock input signal controls both master and slave sections 702,704.

Next, the operation of the circuit 700 will be explained with reference to FIGS. 13 to 16. V (cl, k) waveform 720 (first
4) is smaller than V (m), the output of the master unit 702, which is the highest master load voltage, is fixed regardless of any change in the input at node D. Therefore, it is possible to change nodes A and B only if waveform 720 is greater than V (m).

If the waveform 720 is greater than V(s), the slave section 7 at nodes C and D is the maximum slave load voltage.
The input of 04 provides control independently of the states of nodes A and B. Therefore, it is possible to load the output from the master section 746-O2 into the slave section 704 only when the waveform 720 is less than V(s).

Since circuit 700 is negative edge triggered, V(m) is always greater than V(s). The input to the master section is controlled by clock pulses 720. Clock pulse 720 also regulates the state of coupling transistor 730 connecting master section and slave section 702, 704. Its operation sequence is as follows. At point 732, slave 704 is separated from master 702, at point 734, information is provided from the D input to master section 702, at point 736, the D input is disabled, and at point 738, information is provided from master section 702 to slave section 704. Transfer information to.

The asynchronous inputs for asynchronous clear and reset are: A high input to CLEAR sets Q low, a high input to PRESET sets Q high, and applying high to CLEAR and PRESET simultaneously causes both outputs to go high. Also, asynchronous CLEA
The R and PRESET inputs are connected to flip-flop 700 independently of clock waveform 720, regardless of their previous state.
is forced into a fixed state. CLEAR and PRES
The ET input is a series of CL E A R and PRESET
Even if the inputs are coupled, they are configured to reduce current hogging.

Figure 17 shows the three-man AND game 1-800 and the two-man N game.
FIG. 8 is a block diagram of circuits 800, 802, and 804 each configured with an AND gate 802 and a set 804 of inverters 806. FIG. 18 shows isoplanar I2L, ie, I3L, latch enable circuits 800, 802, 80.
4 details are shown. FIG. 19 shows circuits 800, 80
Waveforms 830, 832, 8 used in 2,804
34 is shown. The three inputs to AND gate 800 generate a signal at node A via AND gate 80C1. The signal at node A is AND gate 8
00 and provides a signal to Node B. NAN
D-gate 802 uses the signals at nodes A and B to generate a 47- negative going pulse 834 at its output 810. The width of this pulse 834 is controlled by the gate delay of inverter 806.

However, the polarity of pulse 834 is
02.

20 and 21 show further details regarding generating the three inputs to AND gate 800 in the latch enable timing circuit of FIG. 17. Clock pulse CP is passed through inverter amplifier 1006 to D
It is supplied to flip-flop circuits 1000, 1002, and 1004.

The system timing signal is wired 1008.101Q, 1
012 through flip-flop 1. OO0-100
4's D input. Wiring 1014. .

Flip-flop 1000-1 on 1016.1018
The -004 Q outputs constitute the three inputs to AND gate 800. These Q outputs are also wired 1012.102
2,1024 to the AND game 1-1026. AND gate 1026 connects register file 82
D flip-flop 700 (12th
An additional set of A pulses is provided on wire 1028 to trigger edges 49-48- (FIG.). FIG. 21 shows the timing relationship between clock pulse CP and the A and B pulses.

From the foregoing, it will be appreciated by those skilled in the art that there is provided a novel high performance microprocessor integrated circuit and improved circuitry for incorporation within such a microprocessor integrated circuit capable of achieving the objects of the invention as set forth above. It is thought that this has become clear to people like him. The ROM configuration of the present invention allows efficient layering within integrated circuit 50 and allows for rapid access to microcode stored within the ROM. (2) Maintaining proper bias conditions throughout the 2L integrated circuit 50 while reducing the width of the injection bus. The data path multiplexing and bus operating configuration of the present integrated circuit 50 allows it to provide improved performance. The configuration of register file cell 900 allows significant savings in chip size and power requirements.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited only to these specific examples, and various modifications may be made without departing from the technical scope of the present invention. Of course, it is possible.

[Brief explanation of the drawing]

1 is an explanatory diagram showing the layout of FIGS. 1A and 1B; FIGS. 1A and 1B are generalized block diagrams of a microprocessor integrated circuit constructed based on the present invention; 2 is a timing generator state diagram for the microprocessor integrated circuit shown in FIGS. 1A and 1B, and FIG. 3 is a timing generator state diagram for the microprocessor integrated circuit shown in FIGS. FIG. 4 is a block diagram of a ROM configured according to the present invention, FIG. 5 is a schematic circuit diagram of a ROM circuit used in the present invention, and FIG. Figure 7 is a schematic circuit diagram of another ROM circuit used in the present invention.
The figure is a schematic circuit diagram of another ROM circuit used in the present invention, FIGS. 8 and 9 are plan views showing the bus configuration used in the present invention, and FIG. 10 is a schematic circuit diagram of another ROM circuit used in the present invention. 11 is a logic circuit diagram of a latch circuit used in the present invention. FIG. 12 is a schematic circuit diagram of a flip-flop circuit used in the present invention. The figure is an explanatory diagram showing a truth table useful for understanding the circuit of FIG. 12, and FIGS. 14 to 16 are waveform diagrams useful for understanding the operation of the circuit of FIG. 11. FIG. 17 is a logic circuit diagram of the timing circuit used in the present invention, the first
Figure 8 is a schematic circuit diagram of the timing circuit in Figure 17;
Figure 19 is a waveform diagram useful for understanding the logic circuit diagram in Figure 17, and Figure 20 is the logic/block diagram of the circuit that generates the inputs to the circuits in Figures 12, 17, and 18. The diagram, FIG. 21, is a waveform diagram useful for understanding the operation of the circuit of FIG. (Explanation of symbols) 51-50: Microprocessor integrated circuit 52: Data processor 54: Microprogram control 56: Address processor 58: Interrupt/Fault processor 60: Timing unit Patent applicant Fairchild Camera and Instrument Corporation 53-52 - ■ 41 reports/l'su 1 blind ■ FIG, I. Great now Rugis 91 FIG, lA l? "Hishiri" +50. PLA 1 Bokujin TelX Shi1-1 71"L2A'f-9 Kurihimo ・841? I hate PLA. 172 183 180 1 ■ Inikudameshita My Qollg 4N) 12/-754
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September 12, 2015 [phase] United States (US) 1 @ Participant Richard Pan Amesarao Inventor Hemler Kay, Hin Amegar Ura [Co., Ltd.] 530995 seconds 530996 seconds 530997 United States, California 94086. Sunny Bell. 813 Wolf Road, United States, California 95121. San Jose. T-end coat 3446

Claims (1)

[Claims] 1. A microprocessor integrated circuit comprising a register file having a first plurality of registers, wherein the first
A circuit characterized in that each of the plurality of local buses is connected to one of the second plurality of local buses, said local buses being connected to the main bus by multiplexing means. 2. In claim 1, an address decoder for selecting a register connected to each of the local buses; and a second address decoder for selecting one of the second plurality of local buses. A circuit characterized by having: 3. A microprocessor integrated circuit having a main injection bus, having a ground return bus, at least one branch ground bus, and a ground balance resistor connecting the ground return bus to the branch ground bus. Featured circuit. 1-4. The circuit of claim 3, wherein at least one branch injection bus is connected to the main injection bus by an injection drop resistor. 5. Claim 4, wherein a plurality of branch injection buses are each connected to both ends of the main injection bus via injection drop resistors, and each branch injection bus is provided with a plurality of branch ground buses. ground return buses are provided, each branch ground bus being connected to its main ground bus via a ground balance resistor, and wherein the branch ground bus and the branch injection bus are intermeshed with each other. circuit. 6. In a memory storage circuit having a latch, a pair of output terminals, a data input terminal to the latch, an enable signal input terminal for controlling the data input to the latch, each one of the pair of output terminals; and a pair of output enable signal input terminals connected to control the output enable signal. 7. In claim 6, the circuit is coupled to a circuit for generating the enable signal input 2- in response to a clock signal, the width of the enable signal being established to transmit the desired data to the A circuit characterized by latching within a memory storage circuit. 8. A microprocessor integrated circuit comprising a register file having a first plurality of registers, each of said registers being connected to one of a second plurality of local buses, said local bus being connected to one of a second plurality of local buses; connected to a main bus, at least some of the first plurality of registers having a memory storage circuit, the memory storage circuit having a latch, the latch having a pair of output terminals and a a data input to the latch; an enable signal input for controlling the data input to the latch; and a pair of output enable signal inputs each connected to control one of the pair of outputs. A circuit characterized by: 9. In claim 8, the main injection bath;
A circuit comprising a ground return bus, at least one branch ground bus, and a ground balance resistor connecting the ground return bus and the branch ground bus. 10. In a D-type flip-flop circuit equipped with a master section and a slave section, the introduction of data from the D input terminal to the master section is controlled by a clock input, and input terminals for rear and preset input terminals are independent of the clock input. operative to set a desired state for a pair of outputs from said flip-flop circuit from any previous state. 11. In a timing circuit for enabling a latch circuit, a delay means is connected to receive a timing pulse from a timing pulse generation means, and the timing pulse generation means has a plurality of inputs for generating the timing pulse. and the delay means is connected to provide a first delayed timing pulse to the output gate, and the timing pulse generating means is also connected to provide a second delayed timing pulse to the output gate. A circuit connected to provide a timing pulse, wherein a latch enable j- signal is provided as an output from said output gate. 12. In claim 11, a plurality of inputs to the timing circuit are provided by a plurality of D-type flip-flop circuits controlled by clock pulses, and wherein the plurality of D-type flip-flop circuits are controlled by clock pulses. 2. A circuit connected to supply said plurality of inputs to a two output gate, wherein a trigger pulse for an additional flip-flop circuit is supplied as an output from said second output gate. 13. In claim 12, the additional flip-flop circuit has a master section and a slave section, and the introduction of data from the D input terminal to the master section is controlled by the trigger pulse. and a preset input independent of the clock input sets a desired state for the pair of outputs from each of the additional flip-flop circuits from any previous state. circuit. 5-14=14. A microprocessor integrated circuit having a timing circuit for enabling a latch memory circuit in a register file of the microprocessor, wherein said timing circuit is connected to receive timing pulses from a timing pulse generating means. , wherein the timing pulse generating means is connected to receive a plurality of inputs for generating the timing pulse, and the delay means transmits the delayed timing pulse as a first input to an output gate. the timing pulse generating means is further connected to provide an undelayed timing pulse as a second input to the output gate, and the latch enable signal is connected from the output gate to the latch memory. A circuit characterized in that it is supplied as an output to a storage circuit. 15. In claim 14, also within the register file, the D-type flip-flop memory storage circuit has a master section and a slave section, and the input terminal from the D input terminal to the master section 6- Data introduction is controlled by a clock input, and an input and preset input independent of the clock input functions to set the desired state for the pair of outputs from the flip-flop circuit from any previous state. A circuit characterized by: 16. In claim 14 or 15,
The plurality of inputs to the timing circuit are provided by a plurality of D-type flip-flop circuits controlled by clock pulses, and the plurality of D-type flip-flop circuits provide the plurality of inputs to a second output gate. , and wherein a trigger pulse for the flip-flop memory storage circuit as described above is provided as an output from said second output gate. 17. In a microprocessor circuit having read-only memory, there is provided a first plurality of X- and Y-addressable memory locations arranged in words, bits, and pages, with a first plurality of X- and Y-addressable memory locations on each page in the A circuit characterized in that the circuit accesses one of a second plurality of words, and in the Y direction one of a third plurality of pages and one of a fourth plurality of bits. 18. The circuit according to claim 17, wherein the read-only memory includes a decoding circuit including a plurality of page selection transistors. 19. The circuit of claim 18, wherein the decoding circuit comprises a programmable storage transistor. 20. Claim 19, wherein the decoding circuit comprises a collector of one of the page select 1-transistors and another one of the emitter-programmable transistors.
1. A circuit comprising: a first reference circuit connected between two emitters; 2. In any one of claims 18 to 20, the page selection transistor is a multi-emitter transistor, and one emitter of the page selection transistor is an output transistor from the decoding circuit to an output transistor. connected to supply the second
A circuit characterized in that the emitter is connected to the base of the transistor and a second reference circuit. 22. In a decoding circuit for a read-only memory, a plurality of multi-emitter page selection transistors are provided, one of the multi-emitters of each page selection transistor is connected to supply an output from the decoding circuit, and each page A circuit characterized in that another one of the multiple emitters of the selection transistor is connected to the base of that transistor and is connected to receive a reference potential. 23. A microprocessor integrated circuit having a register file having a first plurality of registers, each of said first plurality being connected to one of a second plurality of local buses, said local bus having multiple registers. operating means connected to the main bus, at least some of the first plurality of registers having memory storage circuitry, the memory storage circuitry having a latch; The latch has a pair of outputs, a data input to said latch, an enable signal input for controlling said input to said latch, and a pair of output enable terminals each connected to control one of said pair of outputs. a signal input terminal, further comprising a main injection bus, a ground return bus, at least one branch ground bus, and a ground balance resistor connecting the ground return bus and the branch ground bus; At least some of the registers in the register file are formed from D-type flip-flops with a master part and a slave part, the introduction of data from the D input to the master is controlled by a clock input, 2. A circuit according to claim 1, wherein a clock input and a preset input, independent of the clock input, function to set a desired state for the pair of outputs from the flip-flop circuit from any previous state. 2. In claim 23, some of the registers in the register file are formed from memory storage circuits, the memory storage circuits having latches, and the latches comprising: a pair of outputs, a data input to said latch, an enable signal input for controlling said data input to said latch, and a pair of output enables each connected to control one of said pair of outputs; A circuit characterized in that it comprises a signal input terminal. 2. Claim 24, wherein a timing circuit is provided for enabling the latch memory circuit in the register file of the microprocessor, and the timing circuit receives a timing pulse from a timing pulse generating means. a delay means connected to receive a plurality of inputs for generating the timing pulse; and wherein the delay means is connected to receive a plurality of inputs for generating the timing pulse; the timing pulse generating means is further connected to provide a second non-delayed timing pulse to the output gate, and the latch enable signal is connected to provide a second delayed timing pulse to the output gate; A circuit characterized in that it is provided as an output from an output gate to the latch memory storage circuit. 2. In any one of claims 23 to 25, a read-only memory is provided, the read-only memory comprising a first memory arranged in the form of words, bits and pages. having a plurality of X and Y addressable memory locations, addressing one of the second plurality of words on each page in the X direction and one of the third plurality of pages and one of the third plurality of pages in the Y direction; A circuit characterized in that it addresses one of a fourth plurality of bits. 2. In claim 26, a decoding circuit for the read-only memory is provided, the decoding circuit having a plurality of multi-emitter page selection transistors, and a multi-emitter transistor for each page selection transistor. one of the emitters is connected to provide an output from the decoding circuit, and another one of the multi-emitters of each page select transistor is connected to the base of that transistor and connected to receive a reference potential; A circuit featuring: