JPS609141A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS609141A
JPS609141A JP58117318A JP11731883A JPS609141A JP S609141 A JPS609141 A JP S609141A JP 58117318 A JP58117318 A JP 58117318A JP 11731883 A JP11731883 A JP 11731883A JP S609141 A JPS609141 A JP S609141A
Authority
JP
Japan
Prior art keywords
tape
wafer
layer
chips
collet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58117318A
Other languages
Japanese (ja)
Inventor
Akinori Tanizaki
谷崎　昭典
Noboru Ando
昇 安藤
Satoshi Terayama
智 寺山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58117318A priority Critical patent/JPS609141A/en
Publication of JPS609141A publication Critical patent/JPS609141A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent generation of the breakage of tape on which a wafer is adhered even when the wafer is completely cut at the scribed part by a method wherein a two-layer structure tape, which is formed by superposing the tape material having two different kinds of properties. CONSTITUTION:The second layer tape 12 which comes in contact with a wafer 11 is formed using vinylidene chloride resin and the like having strong adhesive power and easy-to-break property but having no extending property, and the first layer tape 13 is formed using the material having a high degree of polymerization. A two-layer structure tape is formed by adhering the above-mentioned tapes. Said wafer 11 is adhered to the second layer tape 12, it is divided into chips 11a by cutting it along scribe lines. These chips 11a are vacuum-attracted by performing an evacuation using a collet, for example, and they are removed from the tape 12. At this time, the second layer tape 12 is broken and left on the tape 13 in the state of attraction, and the chips 11a only are removed from the tape 12 and attracted to the collet.

Description

【発明の詳細な説明】 （１１発明の技術分野 本発明は半導体装置の製造方法、詳しくはウェハをテー
プ構造体にはりつけ完全にチ・ノブ毎にスクライブしく
切込みを作り）、そのテープを均一に拡張し、しかる後
にチップを次の組立工程に移し替える方法に関する。DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device, in which a wafer is attached to a tape structure, and a cut is made in a scribe manner for each chi/knob. It relates to a method for expanding and then transferring the chip to the next assembly process.

（２）技術の背景 ウェハプロセスの終了したウェハはウェハに設けたスク
ライブラインに沿ってスクライブして個々のチップに分
割し、これら個々のチップを次の組立工程に移し替えて
所定の半導体装置を製作するニー前記したウェハのスク
ライブに際しては、ウェハを粘着テープにはりつけた上
でスクライブするが、従来このスクライブはウェハの厚
み全体に切り込むことなく、５０％２程度切り込んでか
ら個々のチップに割る方法がとられていた。(2) Background of the technology After the wafer process has been completed, the wafer is divided into individual chips by scribing along the scribe lines provided on the wafer, and these individual chips are transferred to the next assembly process to form predetermined semiconductor devices. When scribing the wafer described above, the wafer is attached to an adhesive tape and then scribed, but conventionally this scribe method does not cut through the entire thickness of the wafer, but instead cuts about 50% of the wafer and then breaks it into individual chips. was taken.

ところがウェハを前記の如くに割った場合にかけらや粉
粒が発生し、それがチップ上に付着しそのチップを不良
にする問題が経験され、それを防止するため最近はウェ
ハの厚み全体にわたって完全にスクライブする方法がと
られるようになってきた。However, when the wafer is broken as described above, particles and particles are generated, which adhere to the chips and cause the chips to become defective. The method of scribing has started to be used.

（３）従来技術と問題点 前記した如くにウェハを完全にスクライブすると、その
ときに粘着テープにも切込みがなされ、粘着テープに裂
は目（破れ）が形成される。個々のチップはコレットを
用いて次の工程に移されるのであるが、そのとき個々の
チップの間に空隙を作るために粘着テープが拡張される
。そうすると、粘着テープは裂は目や切れ目に沿って破
れ、その結果ウェハの形状が乱され、チ・ノブ相互間の
ピ・ノチが乱れまた場合によってはチップがバラバラに
なり、チップの次工程への移し替えに支障を来す問題が
ある。(3) Prior Art and Problems When a wafer is completely scribed as described above, cuts are also made in the adhesive tape, and tears are formed in the adhesive tape. The individual chips are transferred to the next process using a collet, during which time the adhesive tape is expanded to create gaps between the individual chips. When this happens, the adhesive tape tears along the lines and cuts, which disturbs the shape of the wafer, disturbs the tips between tips and knobs, and in some cases breaks the chips apart, allowing them to be transferred to the next process. There is a problem that hinders the transfer of

（４）発明の目的 本発明は上記従来の問題点に鑑み、ウニ／Ｓのスクライ
ブにおいて、ウェハは完全に切断するがウェハをはりつ
けたテープの破れ（切れ）が発生することのないウェハ
スクライブ方法を提供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a wafer scribing method that completely cuts the wafer but does not cause tearing (cutting) of the tape to which the wafer is attached during scribing of sea urchin/S. The purpose is to provide

（５）発明の構成 そしてこの目的は本発明によれば、ウェハをチップ毎に
完全切断し次工程に移す方法において、拡張可能な第１
層テープに粘着性はもつが拡張性をもたない第２層テー
プをはりつけて２層構造のテープ体を作り、ウェハを前
記第２Ｎテープにはりつけてチップ毎に完全切断し、し
かる後に第１層テープを拡張しチップを移し替えること
を特徴とする半導体装置の製造方法を提供することによ
って達成される。(5) Structure and object of the invention According to the present invention, in a method of completely cutting a wafer into chips and moving to the next process, an expandable first
A second layer tape that has adhesiveness but no expandability is attached to the layer tape to create a tape body with a two-layer structure, and a wafer is attached to the second N tape and completely cut into chips. This is achieved by providing a method for manufacturing a semiconductor device characterized by expanding a layer tape and transferring chips.

（６）発明の実施例 以下本発明実施例を図面によって詳説する。(6) Examples of the invention Embodiments of the present invention will be explained in detail below with reference to the drawings.

従来の粘着テープについて第１図の模式的断面図を参照
して説明すると、粘着テープＩまたはウェハ２を加熱し
てウェハ２を粘着テープ１にはりつけ、ダイヤモンドソ
ーまたはダイヤモンドブレードを用いてウェハ２を個々
のチップ２ａ毎に切断した。そのとき３、粘着テープ１
が図に示されるように部分的に切り込まれ、これが粘着
テープ１が破れる原因であった。A conventional adhesive tape will be explained with reference to the schematic cross-sectional view in FIG. It was cut into individual chips 2a. At that time 3, adhesive tape 1
was partially cut as shown in the figure, which caused the adhesive tape 1 to tear.

そこで本発明においては、第２図の模式的断面図に示さ
れる如く、２層構造のテープ体を用いる。Therefore, in the present invention, as shown in the schematic cross-sectional view of FIG. 2, a tape body having a two-layer structure is used.

すなわち、ウェハ１１と接する第２Ｍテープ１２は、粘
着力は強いが拡張性がな（破れ易い材料（例えば商品名
サランランプなる塩化ビニリデン樹脂）で厚さ０．０５
〜０．１１に作り、ウェハ１工と接しない第１Ｎテープ
１３は重合度の高い材料（例えばエレクトロンテープな
る商品名のもの）で厚さ０．１〜０．２ｍｍに作り、こ
れらのテープをはり合せて２層構造のテープ体を作゛る
。That is, the second M tape 12 in contact with the wafer 11 has a strong adhesive force but is not expandable (it is made of a material that is easily torn (for example, vinylidene chloride resin, trade name Saran Lamp) and has a thickness of 0.05 mm.
The first N tape 13, which is not in contact with the wafer 1, is made of a material with a high degree of polymerization (for example, one with the trade name Electron Tape) and has a thickness of 0.1 to 0.2 mm. Glue them together to create a two-layered tape body.

ウェハ１１を第２図に示す如く第２層テープ１２にはり
つけて、ウェハをスクライブラインに沿って第３図の模
式的平面図に示す如〈従来技術を用いて切断して個々の
チップｌｌａに分割する。このチップＩｌａが例えばコ
レットを用いて次の工程へ移される。The wafer 11 is attached to the second layer tape 12 as shown in FIG. 2, and the wafer is cut along the scribe line into individual chips using conventional techniques as shown in the schematic plan view of FIG. To divide. This chip Ila is transferred to the next step using, for example, a collet.

第４図にはコレット１４の一部が断面図で示され、図に
矢印で示す方向に排気してチップｌｌａを真空吸着して
テープ１２から外す。そのためには、チップｌｌａ相互
間の図にＷで示す距離が０．５　ｍｍ程度必要で、この
間隔が形成されていないとコレン１−１４の先端縁部分
が第４図に示す如くチップ相互間に入り込むことができ
ない。FIG. 4 shows a part of the collet 14 in cross section, and the collet 14 is evacuated in the direction indicated by the arrow in the figure, and the chip lla is vacuum-adsorbed and removed from the tape 12. In order to do this, a distance of about 0.5 mm between the chips lla, shown as W in the figure, is required. If this distance is not formed, the tip edge of the collen 1-14 will be separated between the chips as shown in Fig. 4. can't get into it.

そこで、第５図の模式的断面図に示される如（、同心円
状の２個のリング１５．１６の間に挾まれた第１層テー
プ１３と第２層テープの２層構造のテープ体を中空筒状
体１７で下方から押し上げる。なお図には簡略のため第
１層テープ１３のみを示す。そうすると、第１層テープ
１３は第３図に見て放射状に外方に向けて拡げられ、個
々のチップｌｌａは第５図に誇張して示す如く互いにほ
ぼ等しい間隔で分離され、この状態で個々のチップｌｌ
ａを第４図に示す如くコレット１４を用いて第２層テー
プ１２から外し、次工程へ移す。Therefore, as shown in the schematic cross-sectional view of FIG. It is pushed up from below by the hollow cylindrical body 17. For simplicity, only the first layer tape 13 is shown in the figure. Then, the first layer tape 13 is expanded radially outward as seen in FIG. The individual chips lla are separated from each other at approximately equal intervals as shown exaggeratedly in FIG.
A is removed from the second layer tape 12 using a collet 14 as shown in FIG. 4, and transferred to the next step.

第１層テープ１３は拡張性があり、またそれ自体はなん
ら切込みや破れがないから、それは第５図に示される如
く拡張されても破れたりすることはない。他方、第２層
テープ１２は粘着性はあるが拡張性がなくさけ易いもの
であるので、第５図の拡張された状態で切込み線または
裂は目に沿って破れることになる。しかし、チップｌｌ
ａがコレット１４によって真空吸着されるとき、コレッ
トの吸着力を適宜設定すると、破れた第２層テープ１２
は第１層テープ１３に吸着したままで残り、チップＬｌ
ａのみが第２Ｎテープ１２から外れてコレットに吸着さ
れる。Since the first layer tape 13 is expandable and does not itself have any cuts or tears, it will not tear when expanded as shown in FIG. On the other hand, since the second layer tape 12 has adhesive properties but is not expandable and is easy to avoid, the score line or tear will tear along the grain in the expanded state shown in FIG. But the chip ll
When a is vacuum-adsorbed by the collet 14, if the adsorption force of the collet is set appropriately, the torn second layer tape 12
remains adsorbed to the first layer tape 13, and the chip Ll
Only part a comes off the second N tape 12 and is attracted to the collet.

上記の実施例ではテープ全面を２層構造にしたが、本発
明の他の実施例においてはうエバ１１の背面に予め第２
層テープ１２をはりつけておき、次いで第２層テープ１
２を第１層テープ１３にはり合せてもよい。In the above embodiment, the entire surface of the tape has a two-layer structure, but in other embodiments of the present invention, a second
The layer tape 12 is pasted, and then the second layer tape 1 is pasted.
2 may be attached to the first layer tape 13.

」二記いずれの実施例においても、第２層テープ１２は
チップｌｌａを保持し、第１層テープ１３は拡張した場
合に破れることがないから、ウェハを完全に切断した状
態で拡張することが可能になる。In both embodiments, the second layer tape 12 holds the chips lla, and the first layer tape 13 does not tear when expanded, so it is possible to expand the wafer with the wafer completely cut. It becomes possible.

また、背面があれたウェハや、金属膜をはりつりたウェ
ハに対しても、上記に説明した２層構造のテープ体を利
用することが可能である。Furthermore, the above-described two-layer tape structure can be used for wafers with a rough back surface or wafers on which a metal film is bonded.

（７）発明の効果 以上詳細に説明した如く、本発明の方法によれば、ウェ
ハのスクライブおよび切断されたチ・ノブの次工程への
移し替えにおいて、従来の１層の粘着テープに代えて２
種類の異なった性質をもつ材料で第１層と第２層のテー
プを重ね合せた２層構造のテープ体を用いることによっ
て、ウェハを完全にスクライブした場合に、チップを次
工程へ移すについて２層構造のテープ体を拡張したとき
、ウェハと接触した第２層テープは破れても第１層テー
プは破れることがないから従来例における如きテープの
破れが防止され、半導体装置製造歩留りの向上に効果大
である。(7) Effects of the Invention As explained in detail above, according to the method of the present invention, the conventional single-layer adhesive tape can be used in scribing wafers and transferring cut chi-nobu to the next process. 2
By using a two-layer tape body consisting of a first layer and a second layer of tape made of materials with different properties, it is possible to transfer the chips to the next process when the wafer is completely scribed. When a tape body with a layered structure is expanded, even if the second layer tape in contact with the wafer is torn, the first layer tape will not be torn, which prevents the tape from breaking as in the conventional example, and improves the semiconductor device manufacturing yield. It is highly effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の粘着テープを用いウェハをスクライブし
たときのウェハと粘着テープの断面図、第２図は本発明
の方法の実施に用いる２層構造のテープ体とウェハの断
面図、第３図はスクライブされたウェハの平面図、第４
図はコレットの先端縁部分の断面図、第５図は２層構造
のテープ体を拡散した状態を示す断面図である。 １１−ウェハ、１２−第２Ｎテープ、１３−第１層テー
プ、１４−コレット、１５．１ローリング、１７−中空
円筒体 第１図 第２図 第３図 第４図 第５１；／：！FIG. 1 is a cross-sectional view of a wafer and adhesive tape when a wafer is scribed using a conventional adhesive tape, FIG. 2 is a cross-sectional view of a two-layered tape body and a wafer used in the method of the present invention, and FIG. The figure is a top view of the scribed wafer, the fourth
The figure is a cross-sectional view of the tip end portion of the collet, and FIG. 5 is a cross-sectional view showing a state in which a two-layered tape body is diffused. 11-Wafer, 12-2nd N tape, 13-1st layer tape, 14-collet, 15.1 rolling, 17-hollow cylinder Figure 1 Figure 2 Figure 3 Figure 4 Figure 51;/:!

Claims (1)

【特許請求の範囲】[Claims] ウェハをチップ毎に完全切断し次工程に移す方法におい
て、拡張可能な第１Ｍテープに粘着性はもつが拡張性を
もたない第２層テープをはりつけて２層構造のテープ体
を作り、ウエノ１を前記第２層テープにはりつけてチッ
プ毎に完全切断し、しかる後に第１層テープを拡張しチ
・ノブを移し替えることを特徴とする半導体装置の製造
方法。In this method, the wafer is completely cut into chips and transferred to the next process.A second layer of tape that has adhesiveness but does not have expandability is attached to the expandable first M tape to create a two-layer tape body. 1 to the second layer tape and completely cut into chips, and then the first layer tape is expanded and the chi knobs are transferred.
JP58117318A 1983-06-29 1983-06-29 Manufacture of semiconductor device Pending JPS609141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58117318A JPS609141A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58117318A JPS609141A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS609141A true JPS609141A (en) 1985-01-18

Family

ID=14708780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58117318A Pending JPS609141A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS609141A (en)

Similar Documents

Publication Publication Date Title
US5897743A (en) Jig for peeling a bonded wafer
JP2007109927A (en) Method and device for peeling surface protection film
JP2008300521A (en) Semiconductor wafer and its processing method
JP2009523099A (en) Cover tape and manufacturing method
US3698076A (en) Method of applying leads to an integrated circuit
JP2000040678A (en) Manufacture of semiconductor chip, and dicing tape
JP2521459B2 (en) Method of manufacturing semiconductor chip
JPS609141A (en) Manufacture of semiconductor device
JPH02170552A (en) Method of dividing semiconductor substrate
JPH02138755A (en) Manufacture of semiconductor device
JPH04367250A (en) Manufacture of semiconductor chip
JP2000305462A (en) Multilayered label and its production
JPS59188940A (en) Adhesive sheet
JPS6181652A (en) Dicing film
JP2683811B2 (en) Masking tape and method for manufacturing semiconductor device using the same
JPS59219376A (en) Adhesive tape for wafer
JPS644339B2 (en)
JPH0157661B2 (en)
JPH01154712A (en) Semiconductor wafer mounter
JPH02191358A (en) Processing of semiconductor device
JPH0348443A (en) Dicing of semiconductor wafer
JP2003027022A (en) Double-sided self-adhesive pad-mounting tape
JPS6042846A (en) Dicing method for semiconductor wafer
JPH03159153A (en) Division of semiconductor substrate
JPH0447960Y2 (en)