JPS6089977A - Field effect transistor - Google Patents

Abstract

PURPOSE:To eliminate the adverse influence of a semiconductor substrate by forming a P type low density buffer layer, a buffer layer region which has two layers of the P type buffer layer and another buffer layer hetero bonded to the P type buffer layer and electrodes on the substrate which has high density active layer. CONSTITUTION:An iron-doped P<-> type GaAs buffer layer 11 is formed by vapor phase growing method on a semi-insulating GaAs substrate 10, and a GaAlAs buffer layer 12 of hetero junction and a GaAs active layer 13 are continuously grown. Then, an aluminum film 21 which becomes a gate electrode formed by an aluminum side etching method using a photoresist is formed on a mesa, AuGeNi layer 22 which become source and drain electrodes are laminated, and alloyed. Then, electrode wirings 23 for connecting the source and drain electrodes to be formed next via bonding pads are formed, and an Au film 24 and the gate are bonded. Thus, the emission of electrons on the surface of the layer 13 can be reduced to eliminate the adverse influence of the substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor using a compound semiconductor.

Compound semiconductors are often used in ultrahigh wave devices due to their physical characteristics. Among these, field effect transistors (hereinafter simply referred to as FETs) using GaAs, which is a 111-V group binary compound semiconductor, have recently made remarkable progress and are being mass-produced. At this stage, it is necessary to obtain high-performance, low-cost ultra-high frequency devices with a high yield.

One element of this is the nature of the buffer layer and the buffer 1
How to increase the abruptness of the concentration profile at the interface between the layer and the active layer has become an important issue in improving performance.

Conventionally, in order to eliminate the negative influence from the semi-insulating substrate, GaAsFETs are made by forming a low-concentration, high-resistivity P-type layer (a single layer of PE) of about 7 to 8 μm, and then layering an n-type QaA layer on top of it.
A generally known structure is that an s-active layer is successively formed by vapor phase growth, and then gate, source, and drain electrodes are formed.

However, in the case of having a single layer of P- GaAs buffer 1, unlike a single layer of n- GaAs buffer, the concentration profile at the interface of the active layer is steep, but the potential still changes slowly and electrons are A phenomenon of seepage into the buffer layer occurs. This has caused a problem in that it causes the gn to fall down and deteriorates the NF in high frequency characteristics.

The purpose of the present invention is to avoid the negative effects from semi-insulating substrates,
Moreover, it is an object of the present invention to provide a high-performance field effect transistor having a buffer layer in which the interface profile between the buffer layer and the active layer becomes more abrupt.

The field effect transistor of the present invention has a buffer 1 layer on a semi-insulating substrate, which is composed of two layers: a P-type low-concentration, high-resistivity GaAs buffer layer, and a GaAIAS buffer layer heterojunctioned with the buffer 1 layer. High concentration of Qa A
A source electrode and a drain electrode which are in ohmic contact with a gate electrode having a Schottky junction are formed on a semiconductor substrate having an active layer.

According to the present invention, the second J@th heterojunction
By using one layer of lAs buffer, GaAlAs
A sharp potential barrier against electrons is formed due to the difference in band gap between GaAs and GaAs, and the seepage of electrons at the interface of the active layer, which has been a problem in the past, is reduced, and performance improvements such as GM can be realized. Moreover, the first
By using a single layer of P-GaA and a single layer of s-buffer, good 1AsB'Hf' can be achieved without suffering from adverse effects from the semi-insulating substrate.

Hereinafter, one embodiment of the present invention will be described in more detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a conventional GaAsFET. A P'' GaAs buffer layer 11 is formed on a semi-insulating GaAs substrate 10, and lacquer is formed on a part of this buffer layer.A GaAs active layer 13 is formed on the mesa, and a gate electrode 21° is formed on the mesa. Source and drain electrodes 22 are formed.

FIG. 2 shows the cross-sectional structure of the epitaxial sea urchin used in the GaAlAs ET of the present invention.

Iron-doped P-G on semi-insulating GaAs substrate 10
aAs buffer) So 11 is formed by a vapor phase growth method (growth temperature near 50° C. shrimp layer = 7 μm).

Next, the Peter junction G using the molecular beam epitaxial method was
aA11A8by7y12 (growth temperature [: 600℃
, shrimp layer: 0.5μrn) and GaAs 7rif (;Q
m13 (shrimp thickness: 0.2 μm, carrier concentration: 2
Next, as shown in FIG. 3, after forming a mesa, side-etching of 7-Al using a photoresist is performed to form an AI that will become a gate electrode.
2] (Al 450ON) is formed on the mesa). Next, as shown in FIG. 4, using a photoresist or using the 7-to-7 method, AuGe NN mackerel 22-(2)Σ15oo'A, ut which will become the source and drain electrodes on the mesa.
=4ooX) and formed by laminating alloy (4308C)
I do. Next, as shown in FIG. 5, a lift-off method using photoresist is used to connect the source and drain electrodes formed on the mesa to each bonding pad. ('I'i
=2000X, Pt=2ooo, K),
Then II! l) A u24 is formed by the rl method.

At this time, gate bonding -5= Pads are also formed at the same time.

As described above, according to the GaAsFBT of this example, P
- a GaAs buffer and a GaAlAs buffer;
By using 7A, the electron output at the interface of the active layer, which has been a problem in the past, is reduced.
Furthermore, a good GaAsFET can be obtained without being adversely affected by the semi-insulating substrate.

The GaAsFE 'I' produced in this way and the first
When compared with the conventional GaAsFET shown in the figure, the 6th
As shown in the figure, the distance at 9 m has improved by about 15 inches, and the Nli' at 12 GHz has also improved from 2.4 dB (average 1 shift) to 2.
．． It was improved to 2dB (average value). In the same figure, the hatched line is a characteristic diagram of the conventional FET, and the line without hatching is a characteristic diagram of the FET of this embodiment. The gate length is 0.5μ in both cases.
An FET with a gate width of 280 .mu.m and a source-drain spacing of 2.0 .mu.m was used.

[Brief explanation of the drawing]

-6= Fig. 1 is a sectional view of a conventional 0aAsFET, and Figs. 2 to 5 are sectional views showing an embodiment of the present invention in the order of manufacturing steps. Figure 6 shows GaAsFE of the conventional one and the present invention.
It is a special plot showing the distribution of gIn in T. 10...Semi-insulating 0aAs substrate, 11. River...
p-GaAs buffer, ]2...
(laAdA, sbanner layer, 13...acdip layer, 21...gate electrode, 22...=...
-A, uLle-Ni, 23-kawa Ti-Pt,
24...Au0 7- -A[ri-

Claims (1)

[Claims] A buffer layer region consisting of two layers, a first buffer layer with a low concentration of Pg and a second buffer layer heterojunctioned with the first buffer layer, on a semi-insulating substrate, and a buffer layer region with a high concentration A field effect transistor characterized in that a gate electrode, a source electrode, and a drain electrode are formed on a semiconductor substrate having a high concentration active layer.