JPS6089145A - Data transmission system - Google Patents

Abstract

PURPOSE:To ensure error detection by adding two data signals having contents equal to an address signal and adopting the data when two signals at the reception side are identical in an in-factory centralized control system or the like. CONSTITUTION:When a master device 1 is brought into the transmission mode, data of the identical content is loaded to shift registers 3, 4 and an address signal is loaded to a shift register 5. When the loading of data is finished, a clock signal is inputted to shift registers 3-5 and the data is shifted serially. Moreover, a signal from the shift register 5 is transmitted to a transmission line 38. A sub-device 2 separates a transmitted signal into data and a clock, the data signal and the address signal are shifted sequentially and the data corresponding to the content of the shift registers 3, 4 enters the shift registers 23, 24. The contents of the registers 23, 24 are compared and when they are coincident, the data is adopted and the mode is inverted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transmission system for remote control of industrial robots in factories, etc.

[Prior art]

In data transmission, parity check codes have traditionally been used to detect false alarms. However, error detection using a parity check code cannot check errors of two or more bits. On the other hand, high-voltage power supplies are often switched in factories, and due to the effects of electromagnetic waves generated at that time, there is a high probability that 2 or more bits will be erroneously mixed into the data transmission path of the central control system in the factory. Errors often occur.

There are some things I can't do. If this is left unaddressed, the robot terminal will operate based on incorrect data, which will not only result in the production of defective products, but also lead to an extremely dangerous situation in some cases.

[Summary of the invention]

This invention was made in view of the above problems.
The purpose is to provide a data transmission method that can reliably detect data errors even in cases where the incidence of data errors is high, such as in data transmission in a factory centralized control system. be.

In order to achieve such an object, the present invention transmits two data signals with the same contents added to one address signal, and compares these two data signals on the receiving side and only if they are the same, This data will be adopted.

〔Example〕

Hereinafter, the present invention will be described in detail along with examples.

FIG. 1 is a block diagram for explaining one embodiment of the present invention. 1 indicates a main device, and 2 indicates one of a plurality of sub devices. 3 and 4 are 16-bit shift registers), when the main device 1 is in the transmission mode, data signals with the same content are input in parallel, and when it is in the reception mode, the data signals transmitted from the sub device are input in parallel. Signals are input serially. Reference numeral 5 designates an 8-bit shift register, in which an address signal specifying a sub-device is input from the address signal generator 6 in the transmission mode, and an address signal transmitted from the sub-device is input in the reception mode. is input. Address signal generator 6 selectively outputs the addresses of all sub-devices to shift register 5 or comparator 7. Comparator 7
compares the contents of the shift register 5 and the output of the address signal generator 6, and outputs a logical value "1" to the AND gate circuit 8 if they are the same. A comparator 9 compares the contents of the shift registers 3 and 4, and outputs a logical value rlJ to the other input terminal of the AND gate circuit 8 if they are the same. Also, the content of the data of the comparator 9 is the same as that of the AND gate circuit 2.
It is latched into the silatch circuit 10 by the latch signal from 0.

Reference numeral 11 denotes a transmitting section, which inputs a clock signal from a clock generator 12 via an AND gate circuit 13 and an OR gate circuit 14, and also inputs an address signal and a data signal from a shift register 5, and converts them into Manchester code. It is output to the transmission line 38. A receiving section 16 receives the signal transmitted from the sub-device 2, and separates the Manchester coded received signal into data and a clock. This data is input to the shift register 3, and the clock is input to the AND gate circuit 15.

A counter circuit 17 outputs one pulse after counting a predetermined number of clock pulses from the clock generator 12 obtained via the AND gate circuit 13. 18 is R-
In the 87 lip-flop circuit, the output of the counter circuit 17 is input to the sb and reset terminal, and the output of the OR gate circuit 19 is input to the set terminal. The Q output of the S-S flip-flop circuit 18 is input to an AND gate circuit 13, which gates the clock pulse of the clock generator 12. Note that a gate signal (C) is further input to the AND gate circuit 13. The Q output is an AND gate circuit 20 whose one input is the output of the AND gate circuit 8.
The output of the AND gate circuit 8 and the clock output separated by the receiving section 16 are respectively input to the AND gate circuit 15 and gated. This pot-
The output state of the S flip-flop circuit 18 determines the mode of the main device 1, and when the Q output is a logical value rlJ, that is, when the Q output is a logical value "0", it is in the receiving mode. Conversely, when the Q output has a logical value of "0", it is in the transmission mode.

The sub-device 2 operates a robot, which is a terminal device, based on data sent from the main device 1, and its configuration is almost the same as that of the main device 1.

21 and 22 are a receiving section and a transmitting section. 23 and 24
is a 16-bit shift register, and 25 is an 8-bit shift register. 26 and 27 are comparators, 28 is a latch circuit, 29 is a counter circuit, 30 is an R-8 flip-flop circuit, and 31 is a clock generator. 32 is an address signal generator, which is different from the address signal generator of the main device 1 and outputs only its own address. 33 to 36 are AND gate circuits, and 37 and 38 are OR gate circuits.

Next, the operation of this device will be explained using the waveform diagram shown in FIG. When an initial reset is input to the set terminal of the R-8 flip-flop circuit 18 of the main device 1 via the OR gate circuit 19 at time t1, the Q output is set to a logic value of "1".
”, the main device 1 enters the transmission mode (Fig. 2 (a)
11). Thereafter, at time t2, data with the same contents are loaded into shift registers 3 and 4, and an address signal specifying sub-device 2 is loaded into shift register 5 from address signal generator 6. When the gate of the AND gate circuit 13 is opened by the gate signal (C) at the end point of the data load, the clock signal from the clock generator 12 is input to the shift registers 3 to 6, and the data is serially shifted. Figure 2 (C)). The clock signal is also input to the transmitter 11, which converts the signal from the shift register 5 into a Manchester code and sends it to the transmission line 38. At this time, the clock signal is also input to the counter circuit 11 and counts 40 (16+1).
6+8) When counted, the transmission end signal (Figure 2 (d))
is output, and the Q output of the S-S flip-flop circuit 18 is set to the logical value "0". This changes the main device 1 to the reception mode.

On the other hand, in the sub-device 2, the initial reset is inputted to the reset terminal of the R-8 flip-flop circuit 30 via the OR gate circuit 38 at time t1, and the Q output becomes the logical value "0".
It is now in reception mode (Fig. 2(e)). Therefore, the AND gate circuit 34 is open and the AND gate circuit 33 is closed. Data sent from the main device 1 is received by the receiving section 21 and separated into data and a clock. When this clock is input to the AND gate circuit 34, since the AND gate circuit 34 is open, it is passed through the OR gate circuit 37 to the shift register 23 or 2.
5 is input. On the other hand, the data signal and address signal separated by the receiving section 21 are sequentially shifted based on the aforementioned clock, and the shift registers 23 and 24 are stored in the main device 1.
Data signals corresponding to the contents loaded into the shift registers 3 and 4 are input to the shift register 25, and an address signal corresponding to the contents loaded to the shift register 5 is input to the shift register 25. After that, in the comparator 26, the shift register 23
and 24, and if they are the same, a pulse signal is output to one terminal of the AND gate circuit 36. In the comparator 27, the shift register 25 and the address signal generator 3
Compare the contents of 2 and if they are the same, AND gate circuit 3
A pulse signal is output to the other terminal of 6. therefore,
Only when the contents of the shift registers 23 and 24 match and the contents of the shift register 25 is a correct address, the SAND gate circuit 3B outputs a logical value "1". At this time, the secondary device 2 is in reception mode and j9, R, -8
The Q output of the flip-flop circuit 30 outputs a logical value of "1". Therefore, the AND gate circuit 35 is left open, and the output of the AND gate circuit 36 is input to the latch circuit 28 via the AND gate circuit 35, as shown in FIG. 2(f).
), the contents taken into the comparator 26 at this timing are latched. The contents of the latch circuit 28 are further sent to a controller (not shown) to operate the robot.

The output of the AND gate circuit 35 (FIG. 2(f)) is also input to the set terminal of the S-S flip-flop circuit 30, and at the same time the data is latched into the latch circuit 28, the Q output becomes logic. When the value rlJ is reached, the transmission mode is set.

Next, data is transmitted from the secondary device 2 to the main device 1. The data in this case is, for example, data that reports the results of the previous operation to the main device 1.

The main device 1 issues the next operation command to the sub device 2 according to the data contents. Data transmission from the sub-device 2 to the main device 1 is performed using exactly the same procedure as the data transmission from the main device 1 to the sub-device 2 described above. In addition, the main device 1
The procedure for checking data errors on the side is also the same as the above-mentioned sub-device 2 (
ItlI is performed using the same procedure as the data error check. As long as data is being transmitted between the main device 1 and the sub device 2 without errors, the robot will operate normally, and if a data error is discovered in either device, The data is not latched and sent at the same time.
Since the reception mode is not reversed, the main device can confirm that the data received by the sub device 0 was incorrect.

In such a case, the main device turns off the power to the sub device and stops the operation of the robot.

〔Effect of the invention〕

As explained above, according to the present invention, two data signals with the same content are added to one address signal and transmitted, and the receiving side compares these two data signals and only if they are the same, the corresponding Since the data is used, it is possible to reliably detect false alarms, and if false alarms are detected, measures such as immediately turning off the power can be taken.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram thereof. 3.4,23.24--16-bit shift register, 5,25...Fist 8-bit shift register, 6,32
...Address signal generator, 9.7, 26, 27 - Comparator, 10, 28 - ... Latch circuit, 38...
Φ・Transmission line. Patent applicant: Tadashi Totsuka Male agent: Kazuki Yamakawa (1 person with ζerect)

Claims (1)

[Claims] Two data signals with the same content are added to an address signal specifying the receiving side and transmitted from the sending side to the receiving side, and on the receiving side, the content of the address signal from the sending side matches its own address, and A data transmission method characterized in that the two data signals are compared with each other and the content of the data signal is adopted only when they match.