JPS60127850A - Detecting system of digital data - Google Patents

Abstract

PURPOSE:To reduce the probability of mis-reception by obtaining a value in following to the majority decision logic from plural data obtained through the use of plural detecting clock ulses as a detection output during the period when the same detected result is obtained in one bit of data. CONSTITUTION:A detected data is stored in flip-flops 1, 2 by detecting clock pulses phi1, phi2 at the first half of a bit data section (a). Since the data is stored in a 3D flip-flop 8 by a detection clock pulse, the detected output S is ''0'' at the end of first half of the bit data section (a) and the detected output K goes to ''1'' at the end of the latter half and the information of the bit data section (a) is discriminated as ''1''. An output E of a flip-flop 11 goes to ''0'' at the end of the bit data section and the information is detected without error. When a positive noise N2 is mixed in the bit data section (c), the noise width is narrow comparatively and the level corresponding to 3 detection pulses phi4-phi6 is low level to the two detection pulses, then the end part K of the final detecting output S goes to a high level and no erroneous operation occurs.

Description

[Detailed description of the invention] (b) Industrial application field The present invention relates to a digital data detection method.

(b) Prior art Recently, protocol controllers (
There is active development of controllers with a C2 configuration that not only control data but also control agreements between transmitters and receivers.

Transmission systems using such controllers use dedicated coaxial cables, twisted wire pairs, optical fibers, etc. as transmission means, and also have hardware such as error correction functions from the viewpoint of data protection, which has the disadvantage of being expensive. It's dust.

On the other hand, home automation (HA) and crime prevention.

Systems that transmit small amounts of data at low speeds and at low cost, such as disaster prevention monitoring systems, usually do not have an error correction function to reduce costs. Furthermore, systems that perform low-cost direct data transmission often use existing commercial power wiring, radio waves, infrared rays, etc. as transmission media.
The transmission environment is extremely susceptible to noise.

Therefore, considering that the amount of data is small, these inexpensive transmission systems require a parity check method (
〆Japanese Unexamined Patent Publication No. 55-66193) or method of confirming data consistency by repeatedly sending the same data ←Unexamined Japanese Patent Publication No. 55-66193)
1A4570) has been adopted.

However, if the transmission environment is particularly poor, the transmitted data cannot be received at once, and the transmission must be repeated many times until the transmission/reception is successful, resulting in a slow response.

OBJECTS OF THE INVENTION An object of the present invention is to provide a digital data detection method that allows data to be sent and received without error even in a noisy transmission environment.

B) Structure of the Invention The present invention provides a period during which the same detection result is obtained within one bit of data (C). This configuration is characterized in that a value according to majority logic is obtained from the plurality of data as a detection output.

(e) Example Figure 1 shows the following Manchester code feeling =
FIG. 2 is a waveform diagram for explaining the principle of data and its general decoding (detection) method. Manchester code expresses binary values by associating them with changes in level ζ,
The level change occurs at the center of each beat data section 1a) lb) (c) (d) as shown in CDa in Figure 1. For example, a falling edge (change from high level to low level) is "1".
, rise 11) (change from low level to high level) “
0', and on the receiving side, the first and second detection a# located in the center of the first half and second half of each page are
The data content is detected by detecting the change using the pulse (Pl) (Pl). For example, in the first detection data section (i) of Fig. 1, the first detection clock pulse (
Since a high level is detected by Pt)l2 and a low level is detected by the second detection cloak pulse (Pit-), the data information of the beat data section 1al is detected as '13' from these two detection outputs. Naru.
The detection clock pulses are generated by a digital PLL circuit (2), and this PLL circuit is synchronously controlled by the input data (2) and outputs the first and second detection clock pulses (PI) (
ζ2 control is performed so that Pl is always located at the center between the first half and the second half of each beat data section.

By the way, if the data information becomes inverted from the normal level due to the noise (N1)(Nz)C as shown in the bit data section (c)ld) in FIG. 1, it is detected as a bit error. Further, depending on the manner of noise intrusion, erroneous data may be detected. In these cases (
: Desired data cannot be obtained in either case.

FIG. 2 is a waveform diagram for explaining the detection method of the present invention, in which data (Da) is a normal value in the beat data interval (ma).
C) is in a state where negative polarity noise (N1) has entered. [φ1) (φ2) (φ&) is each beat data section 1a
) (b) (1st, 2nd, 3rd to detect the first half value of cl)
Detection cloak pulse, (φ4) (φ5) (φ6)
is the fourth one that detects the latter half of the value. Fifth. This is the sixth detected Kurodak pulse. (-In Figure 2, if multiple detection outputs are obtained by three detection cloak pulses in each of the first half and second half of each beat data section, the majority logic is taken, so the beat data section i[11cl Noise (like
Even if the data is violated from Nl)l2, the majority logic in the first half becomes a high level, and by combining with the a-level of the majority logic in the second half, the data in this section becomes 1.
It is judged that. In other words, according to the present invention, there is noise t; therefore, even if a part of the data is corrupted, correct data can be easily obtained by C.
It can be played twice.

FIG. 3 shows a detection circuit that achieves the method of the present invention. (1) shows data (Da) at the D terminal (1D)
(2) is the D terminal (0 port; the 1st D free circuit block (11 (3) is the ND gate connected to C as shown in the figure. +41 (51i61 and OR gate (71
This is a majority logic circuit consisting of the 5th D flip-flop (8) and the cloak terminal of the 5-D block loop (8). (φb) is supplied.

The detection pulse train (φa) is the 1st, 2nd, and 2nd pulse trains shown in FIG. 4th. 5th pulse (φ-1(φ2)(φ4)CφS
), and the detection pulse train (φb) consists of the fifth. @6
Consists of pulses (φ5) (φ6).

(10) is an exclusive OR gate whose input is the output of the OR gate (7) and the output of the third D flip-flop 9 (8) - Ql is the exclusive OR gate (H0) of the exclusive OR gate (H0) The output of the detection pulse train (φb) is applied to the D terminal (), and the detection pulse train (φb) is supplied to the fourth D pre-circulation terminal +T>. The fourth D free circuit αB and the exclusive OR gate f+o+ form a judgment circuit that indicates whether or not data has been detected without error. The output of the monitoring circuit is ((
2)-The output of the majority logic circuit (3) is denoted by fs).

Next, the detection circuit of FIG. 3 will be explained with reference to the waveform diagram of FIG. 4.

First, in the first half of the period data section 1a), the first . Second detection Krovk pulse (φ1) (φ2) (; from.

1st. Detection data is stored in 2nd D Friisobubu O-ybu (11+21.Next≦25th detection klovk pulse (
8), the two stored data (Ql) (
Ql) and the three values of the current data, the first half value is the sixth value.
It is stored in the D fringe block θ block (8). Therefore, at the end of the first half of the period data section fat, "Do" is generated as the detection output Is). Similarly, at the end part [k) of the second half of the C-nividat data section fa), the detection output fsl becomes "1". Therefore, in the subsequent circuit (not shown), the period data interval [
The information of al is determined to be "1°. 14. In the subsequent circuit, the second half end portion 1k) (two detection outputs (slf gate means?) is provided, and this gate output (2) is used for judgment. .For example, since the gate output is "1" in ~section fa), the information in this section fal is "1".
It is determined that In this case, as shown in FIG.
1 becomes "Do" at the end of the beat data section, indicating that the information has been detected without error.

Even in the period data section tc) where the data is partially distorted by noise (N1), the waveforms of each part are as shown in FIG. 4, and information is detected without error. FIG. 5 shows a case where positive polarity noise is further mixed into the beat data section 1cl. Figure 5 B) (B) shows negative polarity noise (
N2) noise width is relatively narrow.

Among the parts corresponding to the three detection pulses (φ4) (φ5) (φ6), the -2 detection pulses are at low level, so the final part of the final detection output fsl [kl is high level and no malfunction will occur.

However, as shown in Figure 5 and 1 (D), there is a wide noise (N2) in which the portions corresponding to at least two of the six detection pulses (φ4) (φ5) (φ6) are at a high level. In this case, it is clear that the end part ik of the detection output (ε)
) becomes a low level, the information in the period data section (cl) will be detected incorrectly.At the same time ≦ 2nd, the end part [k] of the output of the 2nd frivbuflow I becomes a high level and is incorrectly detected. (i.e., erroneous reception).

If such wide noise is mixed in, the intended purpose cannot be achieved, but such wide noise is relatively rare.
Incidentally, by setting the interval between the detection black-day pulses to be large, it is possible to suppress the occurrence of malfunctions due to wide noise.

Compared to the detection method shown in FIG. 1, in the present invention, if the probability of erroneous reception in each repeat data section is reduced to )
1-1.

Although the description has been made regarding the detection of data using the Manchester code, the present invention is not limited to this, and is also effective for detecting data using the NRZ code, for example.

(F) Effects of the Invention According to the present invention, the probability of receiving data incorrectly is reduced, so even if the transmission environment is poor, there is less need to repeatedly send data and the response is faster. effective. Also, OR0 (0yclic Redu
The present invention is extremely useful because it requires a very small amount of hardware compared to error correction circuits such as ndancy check.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the Manchester code used in the embodiment of the present invention. Figure 2 is a signal waveform diagram for explaining the detection method of the present invention.a Figure 3 is a circuit diagram showing a detection circuit implementing the method of the present invention.
FIG. 5 and FIG. 5 are explanatory diagrams thereof. (φ1) to (φ6)...Closures for detection. Figure 6 (A) (B) (C) 0-)

Claims (1)

[Claims] (1) Obtain multiple pieces of data using multiple detection pulses during a period when the same detection result is obtained within one bit of data (2) Obtain multiple pieces of data using multiple detection pulses (2) Obtain majority logic (binary logic) from these multiple pieces of data. A digital data detection method characterized in that the detected value is obtained as a detection output.