JPS6087500A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to precisely and easily test of an internal timing and control the evaluation on a mass production line of the internal timing by measuring the timing of the internal timing signal occurrence circuit from an external terminal only with the tester. CONSTITUTION:The internal timing signal occurrence circuits 1-6 generate the internal timing by delaying a signal supplied from an external part to an input terminal 40. A mode decision circuit 20 decides whether an operation mode of a memory integrated circuit is an ordinary operation mode or a measurement mode, in response to the signal supplied from the external part through a input terminal 41. When the mode decision circuit 20 decides the ordinary operation mode, logical ''0'' is outputted and all try state gates 31-36 are inactivated. When the memory integrated circuit is to be tested, the input signal is supplied from the external part to the input terminal 41 so that the mode decision circuit 20 can decide a measurement mode and output logical ''1,'' all try state gates 31-36 are activated, the internal timing is outputted through input/output terminals 50-55 to the external part and the circuit is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit (hereinafter abbreviated as integrated circuit) provided with an internal timing generation circuit for generating timing necessary for the operation of internal circuits.

With the continuous progress of integrated circuit technology, the number of integrated circuits has increased rapidly, and the large scale and capacity of integrated circuits has now become very large scale.
has reached the point where it has been put into practical use. At the same time, there is a strong demand from the consumer side for integrated circuits, especially memory integrated circuits, to have higher performance and higher speed, and this has become the focus of technological development competition.

In order to increase the speed of integrated circuits, manufacturing variations, such as transistor amplification factors and threshold voltages, must be controlled.

It is necessary to optimally design the internal timing by taking into consideration the flip-flop unbalance conditions caused by contact stray capacitance and the like. In addition, the optimally designed integrated circuit
During mass production, we must not neglect to monitor manufacturing variations.
In addition, over a long period of time, there may be process changes to improve mass production, so it may be necessary to collect statistical data on the effects of process changes on internal timing.

Conventional integrated circuits of this type do not have special means for observing internal timing or collecting data during design and mass production, as described above, and instead require circuit simulation using a computer, mechanical probes, or electron beams. It relies on observation (stroboscopic SEM).

In such conventional configurations, computer simulation has limitations in modeling, and observation using mechanical probes and electron beams requires a large amount of time due to the difficulty of the work, both of which are difficult to achieve during mass production. It has the disadvantage that it is practically impossible to collect statistical data on internal timing due to process variations, etc., since it cannot be a useful method for quality control. An object of the present invention is to provide an integrated circuit whose internal timing conditions can be measured accurately and easily.

The integrated circuit of the present invention is a semiconductor integrated circuit equipped with an internal timing generation circuit for generating timing signals necessary for the operation of internal circuits, and has a mode setting that sets a measurement mode based on a signal supplied from the outside. and an internal timing signal output circuit that outputs at least one of the timing signals in a measurement mode, and the internal timing output circuit is connected to an external terminal of the semiconductor integrated circuit.

Next, the present invention will be explained with reference to the drawings.

- FIG. 1 shows an embodiment of the invention. This embodiment includes an internal timing generation circuit 10 consisting of six signal generation circuits 1.2.3.4.5 and 6, a mode determination circuit 20, and 6.
tri-state gates 31° 32.33, 34.3
an internal timing output circuit 30 consisting of 5 and 36;
Two input terminals 40 and 41 and six input/output terminals 50, 51, 52, 53, 54 and 55 are provided.

Figure 1 shows only a part of the internal timing generation part of a randomly accessible memory integrated circuit9.
Most other parts of the memory integrated circuit, such as the memory array, address circuit, sense amplifier, and control circuit, are not related to the essence of the present invention, and other internal timing generation parts overlap in principle with FIG. Therefore, illustration of each is omitted.

Each of the signal generation circuits 1 to 6 is composed of a monostable multivibrator or the like, and receives a signal externally supplied to an input terminal 40, an M column address strobe, a row address strobe, a write enable signal, and an output. Generates internal timing by delaying the enable signal, etc. The hole internal timing generated in this way can be applied to circuits such as those described in the same memory integrated circuit.
It is supplied by means not shown and is used to perform normal memory operations. Each of the internal timings n is also supplied to one input of each of the tristate gates 31-36.

Input/output terminals 50 to 55 (In) to which tristate gates 31 to 36 are connected (In are originally connected to circuits other than the internal timing generation circuit, such as the aforementioned address circuit, sense amplifier, and control circuit, as shown in the figure) The input/output terminals 50 to 55 are the external input terminals of the memory integrated circuit, and the tri-state gates 31 to 36 are used for branching and outputting signals. For external input signals, the valid period does not overlap with the internal timing for external input signals. The address signal to be sent is

The mode determination circuit 20 is adapted to determine whether the operation mode of the memory integrated circuit is a normal operation mode or a measurement mode in response to a signal supplied from the outside via an input terminal 41. The criterion for determination may be the level of the external input signal or the timing.

When the mode determination circuit 20 determines the normal operation mode, the mode determination circuit 20 outputs logic V"0" and deactivates all tristate gates 31 to 36 (
decrease. Therefore, the input/output terminals 50 to 55 function only for supplying input signals. Memory integrated circuits are commonly used in this manner.

When a memory integrated circuit is to be tested, an input signal is externally supplied to the input terminal 41 so that the mode determination circuit 20 determines the measurement mode and outputs a logic "1". At this time, all tristate gates 31~
36 is activated and transmits the internal timing to the input/output terminals 50-55.

These internal timings are outputted to an external device such as a memory function tester via input/output terminals 50 to 55, and are used there for testing. As is well known, a memory function tester is a tester that can perform GO/NOGO text on the functions of a memory integrated circuit at high speed.

In the embodiment described below, the f'L signal supplied to the mode determination circuit 20 is one signal supplied from the outside via the input terminal 41, but the present invention is not limited to this. do not have. That is, Ni+ was mentioned. A plurality of external input signals such as a write enable signal and an output enable signal may be supplied to the mode determination circuit, and the mode determination circuit may determine the operation mode based on these multiple external input signals. . In this case, there is no need to provide a special input terminal to the mode determination circuit for determining the operation mode, and the input terminal used by the memory integrated circuit during normal operation can be used instead.

According to the present invention, with the above configuration, internal timing can be measured using all testers and only from external terminals, so internal timing can be accurately and easily tested, and internal timing/ It becomes possible to evaluate and manage the process on the mass production line.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention. 1, 2.3.4.5.6... Signal generation circuit, 1
o...group internal timing generation circuit, 2o...
Mode determination circuit, 30...Internal timing output circuit, 31.32°33, 34.35.36...
- Tri-state gate, 40.41... Input terminal, 50.51.52.53.54'. 55... Input/output terminal.

Claims (1)

[Scope of claims] In a semiconductor integrated circuit equipped with an internal timing signal generation circuit that generates timing signals necessary for the operation of internal circuits, a mode setting circuit that sets a measurement mode based on a signal supplied from the outside; an internal timing signal output circuit that takes out at least one of the timing signals in the measurement mode;
It is characterized in that it is connected to the external terminal of the integrated circuit. Semiconductor integration (b) path.