JPS6085426U - delay circuit - Google Patents
delay circuitInfo
- Publication number
- JPS6085426U JPS6085426U JP17821983U JP17821983U JPS6085426U JP S6085426 U JPS6085426 U JP S6085426U JP 17821983 U JP17821983 U JP 17821983U JP 17821983 U JP17821983 U JP 17821983U JP S6085426 U JPS6085426 U JP S6085426U
- Authority
- JP
- Japan
- Prior art keywords
- delay circuit
- resistor
- circuit
- variable resistance
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Networks Using Active Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の遅延回路の一例の回路図、第2図は本考
案の一実施例の回路図、第3図は第2図中の可変抵抗回
路を集積回路化した一例のパターン図である。
10・・・入力端子、10′・・・入力配線、11・・
・出力端子、12・・・抵抗、13・・・インバータ回
路、20・・・可変抵抗回路、21・・・電源端子、2
1′・・・電源配線、21″・・・開口部、22〜27
・・・端子、23’、26’・・・開口部、28・・・
出力端子、28′・・・出力配線、29〜31・・・n
チャネルMSOトランジスタ、32〜34・・・ソース
・ドレイン拡散領域、35・・・ゲート配線。Fig. 1 is a circuit diagram of an example of a conventional delay circuit, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is a pattern diagram of an example of an integrated circuit of the variable resistance circuit in Fig. 2. be. 10...Input terminal, 10'...Input wiring, 11...
- Output terminal, 12... Resistor, 13... Inverter circuit, 20... Variable resistance circuit, 21... Power supply terminal, 2
1'...Power supply wiring, 21''...Opening, 22-27
...terminal, 23', 26'...opening, 28...
Output terminal, 28'...output wiring, 29-31...n
Channel MSO transistor, 32-34... Source/drain diffusion region, 35... Gate wiring.
Claims (1)
、前記抵抗が並列に配列された複数の絶縁ゲート型電界
効果トランジスタからなる可変抵抗回路から構成される
ことを特徴とする遅延回路。1. A delay circuit having a resistor connected in series to an input, the delay circuit comprising a variable resistance circuit including a plurality of insulated gate field effect transistors in which the resistor is arranged in parallel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17821983U JPS6085426U (en) | 1983-11-18 | 1983-11-18 | delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17821983U JPS6085426U (en) | 1983-11-18 | 1983-11-18 | delay circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6085426U true JPS6085426U (en) | 1985-06-12 |
Family
ID=30386991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17821983U Pending JPS6085426U (en) | 1983-11-18 | 1983-11-18 | delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6085426U (en) |
-
1983
- 1983-11-18 JP JP17821983U patent/JPS6085426U/en active Pending
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