JPS6085426U

JPS6085426U - delay circuit

Info

Publication number: JPS6085426U
Application number: JP17821983U
Authority: JP
Inventors: 義一加藤; 秀雄高橋
Original assignee: 日本電気株式会社
Priority date: 1983-11-18
Filing date: 1983-11-18
Publication date: 1985-06-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の遅延回路の一例の回路図、第２図は本考
案の一実施例の回路図、第３図は第２図中の可変抵抗回
路を集積回路化した一例のパターン図である。１０・・・入力端子、１０′・・・入力配線、１１・・
・出力端子、１２・・・抵抗、１３・・・インバータ回
路、２０・・・可変抵抗回路、２１・・・電源端子、２
１′・・・電源配線、２１″・・・開口部、２２〜２７
・・・端子、２３’、２６’・・・開口部、２８・・・
出力端子、２８′・・・出力配線、２９〜３１・・・ｎ
チャネルＭＳＯトランジスタ、３２〜３４・・・ソース
・ドレイン拡散領域、３５・・・ゲート配線。Fig. 1 is a circuit diagram of an example of a conventional delay circuit, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is a pattern diagram of an example of an integrated circuit of the variable resistance circuit in Fig. 2. be. 10...Input terminal, 10'...Input wiring, 11...
- Output terminal, 12... Resistor, 13... Inverter circuit, 20... Variable resistance circuit, 21... Power supply terminal, 2
1'...Power supply wiring, 21''...Opening, 22-27
...terminal, 23', 26'...opening, 28...
Output terminal, 28'...output wiring, 29-31...n
Channel MSO transistor, 32-34... Source/drain diffusion region, 35... Gate wiring.

Claims

[Scope of utility model registration request]

1. A delay circuit having a resistor connected in series to an input, the delay circuit comprising a variable resistance circuit including a plurality of insulated gate field effect transistors in which the resistor is arranged in parallel.