JPS6084654A - Data transfer processing system - Google Patents

Abstract

PURPOSE:To eliminate a decrease in processing speed and perform data transfer processing without being influenced by the disorder of a bus signal by inhibiting a latch clock and fixing the contents of a latch circuit when data transfer from an input/output device starts. CONSTITUTION:While a service-in (SRVI) signal is at a low level, output terminals of D-FFs 6-8 and a JK-FF9 are at the low level, and a clock signal is supplied to the latch clock terminal of a latch circuit 10 through an AND gate 12. The bus signal is latched in a latch circuit 10 with a clock signal. When the SRVI signal on an asynchronous bus goes up to a high level, the clock signal to the latch circuit 10 is inhibited by the AND gate 12 and the contents of the latch circuit 10 are fixed.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a central processing unit and a main memory connected to a plurality of input/output devices through a channel device having a bus conversion device. In a data processing system that uses an asynchronous bus (second bus) to perform data transfer between devices.

A latch means is provided in the bus conversion device to always latch the asynchronous bus data, and when data transfer from the input/output device starts, the latch is prohibited, the latch output is fixed, and the data transfer process is performed. The present invention relates to a data transfer processing method.

[Conventional technology and problems]

FIG. 1 is a diagram showing the configuration of a data processing system. In Figure 1, ■ is the central processing unit, 2 is the main memory, and 3 is the central processing unit.
is a channel device, 4-0 to 4-n are input/output devices, B
C indicates a bus conversion device, and Buff indicates a data buffer.

In FIG. 1, data transfer between the channel device 3 and the main storage device 2 is performed using the first bus, and data transfer between the channel device 3 and the plurality of input/output devices 4-0 to 4-n is performed using the first bus. Data transfer is performed using the second bus. The bus conversion device BC in the channel device 3 is connected to the above two buses, and data is transferred to each input/output device 4-0 to 4-n. Data buffer B that can store a certain amount of data
I have uff4. The second bus is an asynchronous bus, and the 5RVI signal line (service in signal line) declares that data transfer is in progress. , bus signal lines (address signal lines) necessary for data transfer that are determined at the same time.

A synchronized bus conversion device B having such an asynchronous bus
At e, the 8RVI signal is synchronized.

In this bus conversion device Be, upon confirmation of the synchronized 5RVI signal, data transfer processing between the plurality of input/output devices 4-0 to 4-3 is started. At this time, if the signals on the bus signal line necessary for data transfer are directly used, the bus disturbance directly affects the inside of the bus conversion device Be. Therefore, these signals may be latched within the bus converter Be at the start of the data transfer process and not changed during the data transfer process, but in this method.

The signal on the bus signal line is latched when it is confirmed that the data transfer process has started, compared to the case where the signal on the bus signal line is latched, IKed, and used directly.

There is a problem that data transfer processing becomes slow.

[Purpose of the invention]

The present invention is based on the above consideration, and an object of the present invention is to provide a data transfer processing method that does not slow down data transfer processing even when a latch circuit is used.

[Structure of the invention]

For this purpose, the data transfer processing method of the present invention includes a central processing unit, a main storage device, a channel device having a bus conversion device, a plurality of input/output devices, and a communication device between the main storage device and the bus conversion device. a first bus used for data transfer; and a second bus used for data transfer between the bus conversion device and the plurality of input/output devices;
When data is transferred between the bus converter and the plurality of input/output devices using the bus, signals SR and VI declare that the bus converter is transferring data.
In the data processing system, the bus conversion device synchronizes the signals SR and VI, performs data transfer processing using a silatch means, and sends out the response signal 5RVO after the signals SR and VI are determined. Synchronization means for synchronizing signal 8RVI.

the latch means, a clock supply means for controlling the supply of a latch clock to the latch means, and the response signal 5R;
The clock supply means is configured to inhibit the supply of the latch clock and fix the latch output on the condition that the signal 5RVI is synchronized and determined by the synchronization means. It is characterized by being configured as follows.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a circuit configuration of one embodiment of the present invention.

FIG. 3 is a time chart illustrating the operation of the circuit shown in FIG. 2.

In Figure 2, %5 is the receiver, 6 to 8 are D-FF
, 9 is JK-FF% 10 is yf circuit, 11 to 1
3 is and gate, 14 is noah gate, 15 is 5R
The S-VI signal indicating the VO generation circuit is supplied to the input terminal DK of the D-FF 6 through the receiver 5, and the bus signal is supplied to the input terminal of the latch circuit 1o. The output terminal Q of D-FF6 is the input terminal of D-FF7 and the AND gate 11.
connected to the input terminal of The output terminal Q of D-FF7 is D
-The other input terminal of AND gate 11 that can be connected to the input terminal of FF8 and the input terminal of AND gate 11 is D-F.
It is connected to the output terminal Q of F8, and the output terminal of the AND gate 11 is connected to the input terminal J of JK-FF9 and the NOR gate 14.
Connected to the 0 input terminal. The other input terminal of the Noah Goo H4 is connected to the output terminal Q of the JK-Fl"9. One input terminal of the AND gate 12 is supplied with a clock signal, and the other input terminal is connected to the output terminal of the AND gate 14. The output terminal of the AND gate 12 is connected to the latch clock terminal of the latch circuit 10.The latch circuit IO has its input terminal supplied with the bus signal, and the output terminal of the AND gate 12 is connected to the latch clock terminal of the latch circuit 10.
The bus signal is latched by the output signal of the gate 12. The 5RVO generation circuit 15 generates 5RVO at 2τ after the signal at the output terminal Q of JK-F'F9 becomes high level.
When the RVO signal is set to high level and the signal at the output terminal Q of D-1''F6 becomes low level, the 5RVO signal is set to low level.The 5RVO signal is supplied to the input terminal K of JK-FF9, and The circuit shown in FIG. 2, configured as 0 or more, which is sent to the second bus through the AND gate 13, is provided in the bus control device, and the operation time chart is shown below. FIG.

Next, we will explain the operation of the circuit shown in Fig. 2 at the time shown in Fig. 3.
This will be explained with reference to the chart. 5RVI signal is low
D-FF6 to 8 and JK-FF while at level
Each output terminal Q of 9 is at a low level. Therefore, the output terminal of the NOR gate 14 is at the no-y level, and the other input terminal of the AND gate 12 is at the high level, so that the clock signal is passed through the AND gate 12 to the latch of the latch circuit 10.・Supplied to the clock terminal. Then, the bus signal is transferred to the latch circuit lO by the clock signal.
latched to. When the 8 RV I signal on the asynchronous bus becomes high level, the D-FF is activated by the primary clock signal C1.
6 is set, and then the next clock signal C2fD-
FF7 is set. At this time, since the output Q of the K-FF8 is at a high level, the AND condition of (AND)11 is satisfied, and the JK-FF9 is set by the third clock signal C3. and goo) 11 output terminal, or JK-
While the output terminal Q of the FF 9 is at a high level, the output terminal of the NOR gate 14 is at a low level, so that the clock signal to the latch circuit 10 is inhibited by AND/GO (12).

Therefore, the latch circuit 10 fixes the bus signal latched by the second clock signal C2 as it is.
When 2τ has elapsed since the avo creation path 15&I JK-FF9 was set, the 5RVO signal is set to high level. Therefore, JK-FF9 is reset by the next clock signal C6. Further, when the 5RVO signal is sent to the asynchronous bus, the 5RvI signal is set to low level, and the subsequent clock signals C71C8, C9 cause D-F'F6, 7 .
8 is reset.

When JK-FF9 is reset and then D-FF6 is reset, the output terminal of NOR gate 14 is brought to a high level again, and after clock signal C7, it is again supplied to latch circuit 10 through AND gate 12. Become so. The SR and VO creation circuit 15 is.

5RVI signal is brought to low level and D is set at clock C7.
When -FF6 is reset, the 5RVO signal is set to low level on the condition that D-FF6 is reset.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a latch clock is constantly supplied to the latch circuit of the signal of the bus signal to latch it, and data transfer from the input/output device is started. By disabling the latch clock, the self-response of the latch circuit is fixed, eliminating delays in processing speed caused by the provision of the latch circuit, and allowing data transfer processing to be performed without being affected by bus signal disturbances. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a data processing system. FIG. 2 is a diagram showing the circuit configuration of one embodiment of the present invention, and FIG. 3 is a time chart explaining the operation of the circuit shown in FIG. 2. 1...Central processing unit (CPU), 2...Main storage device. 3... Channel device, 4-0 to 4-n... Input/output device f, 5... Receiver %6 to 8... D -F
F, 9...JK-FF, 10...Latch circuit, 11 to 13...AND gate, 14...NOR gate, 15...5RVO creation circuit, BC...
Bus converter. Patent applicant Fujitsu Limited (1 other person) Representative patent attorney
Kyotani 4 part 711 wood 3 side a list

Claims (1)

[Claims] A central processing unit, a main storage device, a channel device having a bus conversion device, and a plurality of input/output devices. a first bus used for data transfer between the main storage device and the bus conversion device; and a second bus used for data transfer between the bus conversion device and the plurality of input/output devices. and declare that when data is transferred between the bus converter and the plurality of input/output devices using the second bus, the data is transferred by the bus converter. The signal 5RVI is synchronized, and the signal 5RV
In a data processing system that performs data transfer processing using a silatch means and sends out a response signal 5RVO based on the determination of I, the bus converter is configured to perform a synchronization process that synchronizes the signal SVI. the latch means, the clock supply means for controlling the supply of the latch clock to the latch means, and the response means for sending the response signal 5RVQ, and the clock supply means is provided with the signal 5RVI by the synchronization means. A data transfer processing method characterized in that the latch output is fixed by inhibiting the supply of the latch clock on condition that the latch clock is synchronized and determined.