JPS60108954A - Data selecting and transferring system - Google Patents

Abstract

PURPOSE:To transfer immediately data from the transmission sides in output ready state to the receiving side successively starting from the highest priority and to transfer rapidly, asynchronously and selectively the data by providing a data selection and transfer control circuit between the transmission sides having first-in first-out (FIFO) registers and the receiving side. CONSTITUTION:Try state buffers 3-1-3-N are connected to N transmission sides 1-1-1-N having FIFO registers in their insides and the receiving side 2 having an FIFO in its inside is connected to the buffers 3-1-3-N through a common parallel data transfer line 4. The data selection and transfer control circuit 5 is connected between output ready signal OR terminals and shift out signal SO terminals on the transmission sides 1-1-1-N and an input shift signal Si terminal and an input ready signal iR terminal on the receiving side 2. The control circuit 5 is constituted of logical circuits and data are transferred from the transmission sides 1-1-1-N of which outputs are in the ready state to the receiving side 2 successively starting from the highest priority, so that the data are transferred asynchronously, rapidly and selectively.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a data selective transfer method for selectively transferring data from one or more data transmitting sides to one data receiving side asynchronously and at high speed. Equation % [Background of the Invention] It is often necessary to selectively transfer data between memories, or between memories and input/output circuits, or between input/output circuits.

At this time, selective data transfer control is either unnecessarily complicated, or it is impossible to selectively transfer data at high speed. This is because data is transferred in a manner that is synchronized between the data sending side and the data receiving side. In addition, control regarding selective transfer, data amount management, etc. is complicated, and furthermore, because of the synchronous transfer, it is impossible to control data selective transfer at high speed. Even when selective transfer is performed asynchronously, the reality is that complicated controls are required for timing control, data amount management, etc.

[Purpose of the invention]

It is therefore an object of the present invention to
One data receiver with easy control.

Furthermore, the present invention provides a data selective transfer method capable of selectively transferring data at high speed and asynchronously.

[Summary of the invention]

For this purpose, the present invention provides a data output ready signal outputted from either of the data transmitting sides each having a first-in, first-out storage means, and a data input ready signal outputted from a data receiving side each having a first-in, first-out storage means. The transmission data is asynchronously transferred from the data transmitter having the highest priority among the data transmitters that have issued the data output ready signal to the data transmitter.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 3.

First, an example of the data selection transfer system according to the present invention will be explained with reference to diagram m1. In the system configuration of this example, data is selectively transferred from the N data transmitting side having internal first-in, first-out registers (hereinafter referred to as FiFo) 1-1 to 1 to Nf to the data receiving side having internal FiFo2Y. The data is sent to the control F by the control circuit 5 and is intended to be selectively transferred. According to this, FiFo 1
The data from -1 to 1-N can be transferred to the FiFo2 which is in the input ready state via the tristate buffer gates 3-1 to 5-N and the common parallel data transfer path 4.
If there is an output ready signal from any one or more of iFol -1 to 1-H, the pip in the input ready state is selected from the transmission side hapo that has issued the output ready signal, starting with the one with the highest priority.

2, data is transferred asynchronously. In this example, the priorities are set in advance such that FiFo1-1 is the highest and FiFol-N is the lowest, but the data selection transfer control circuit 5 receives an input ready signal from FiFo2.

When there is an output ready signal from FiFol -1 to 1-N, a shift-in signal is given to FiFol 2 so that the signal is read out to the common parallel data transfer path 4. While data is taken in from the item with the highest priority, a shift-out signal is given to the item with the highest priority to prompt the data to be transferred next to be shifted out. be.

Figure 2 shows a specific configuration of an example of a data selection transfer control circuit when there are three data transmitters. As already mentioned, FiF.

When any one of 1-1 to 1-5 becomes capable of outputting data, an output ready signal (OR) is output from that one.

Furthermore, when the FiFO 2 becomes free and ready to receive data, an input ready signal iR is output, and from this point on, the data is transferred to the FiFO 2 according to the necessary handshake procedure.

Here, only the handshake between FLFol -1 and 2 is t
If we think about it, it is only after the output ready signal OR1 is obtained from pipol-1 and the input ready signal cR is obtained from FiFo2, that the shift-out signal OR1 is applied to FiFol-1 and the shift-in signal is applied to FiFo2. A signal Si will be given.

The output ready signal OR1 is a Nant gate (open collector type) 506. The input ready signal iR is outputted as a shift-in signal 5i via a NOR gate so5, and the input ready signal iR is ANDed with the output ready signal ORI via an AND gate 502 and then output as a shift-out signal 501.
This is what is output as. However, in this example, the shake hand is performed only after the transfer start signal 5rxr'' is applied from the outside.As shown in Figure N3, before the time point to when the transfer start signal STAm'' is applied, the input ready signal is The output ready signal OR1 is forcibly suppressed by the inverter 501 and the NOR gate 5o5. However, at one point t
Output ready signal ORI (output ready signal OR
1 (11) and the input ready signal iR are output, and the shift-out signal 501 and shift-in signal 5i are obtained from the time point i1'1 to. Depending on the shift out signal 501, the tri-state buffer gate 3
Since only FiFol -1 is placed in a low output impedance state, data from FiFol -1 is shifted into FiFol 2 at the rising edge of shift-in signal 5i. FLFO2 to which data has been shifted in
Then, in order to determine whether it is necessary to transfer the data to the output side or whether or not it is possible to shift in the primary data, the input voltage signal iR is used until the time t when the input becomes ready again.
is designed to fall once at time t1. Also, pi
In pol-1, the data to be transferred next is shifted out based on the presence of the shift-out signal SO1 and the output ready signal OR1, and the data is output to the tri-state buffer gate 6-1. Until then, the output data is uncertain.

Therefore, output ready signal 0R1 (output ready signal O
R1 (11) is designed to fall once until time t4 when FiFoi-1 becomes ready for output again. If there is no data to be transferred, the output ready signal 0R1 (as shown as 2+) remains low even after time t4.It is output at time t, when a certain period of time has elapsed from the rise of the shift-in signal 5i. Ready signal OR1
, (The output ready signal OR1 (11) is about to fall once.

Note that, prior to the input ready atonement, the shift-in signal Si
may be output, but in such a /L case, the data first becomes FiF when the input ready signal cost is output.
It is now being shifted into o2.

Data transfer is performed as described above when only pipol-1 and pipol-2 are considered, but %FiF.

If 1-2.1-5 is also taken into account, the shift out signal 502 will be based on the output ready signals OR1 and OR2.
, 505 can be controlled. As shown in the figure, the output ready signal OR1 is obtained through the NOR gates 51[) and 512 and the AND gates 508 and 5.
11 is suppressed, the shift out signal 502
, 505 are not output, and while either the output ready signal OR1 or OR2 is obtained, the NOR gate 512 suppresses the 77 do) l-to 511, so the shift out signal 505 is output. It never happens.

In other words, pipol-2 can output data only if FiFol-1 is not in the output-ready state and itself is in the output-ready state.

FiFol-3 can output data only when FiFol-1 and FiFol-1-2 are both not in the output ready state and FiFol-3 itself is in the output ready state. Note that the resistor 514 is used to wire-OR the outputs of the Nant gates 506, 509, and 515 for generating the shift-in signal Si.

By the way, for example, if FiFol-1 becomes output ready while the serial out signal 502 is being applied to FiFol-2, shift-out No. 46 501 will be applied to pipol-1 from that point on, causing problems in the shift-out operation. will occur. Also.

Although there is a possibility that the device that outputs the data will immediately issue an output ready signal again, the output ready signal issued by the device with a lower priority while the output ready signal is falling causes the device to output data. This is a problem because there is a possibility that In order to prevent such a situation, in this example, depending on the shift out signal 502, the NOR gate 507 is
The AND gate 505 is suppressed through
Both AND gates 505 and 508 can be suppressed through 10. Furthermore, V of input ready signal iR
This one-shot circuit 504 (7)) is a handshake prohibition circuit that is triggered at the time of downlink.
Handshaking is prohibited by inputting SK to the NOR gates 507, 510, and 512. The pulse width T of the trigger output MASK is set to be slightly larger than the minimum time required for the output ready signal to rise again, but this is due to the noise
0, 512 via Nandogoo) 506, 509
, 515 and AND gates 505 , 508 , 51
It is designed to suppress 1. therefore,
In FIG. 5, if the first handshake took place at time A to, the second handshake takes place at time t.
, which will be carried out later. In addition.

Although the present invention has been fully described in the case where there are five data transmitters, it is clear that it is applicable not only to the case where there is one data transmitter but also to the case where there are generally two or more data transmitters).

〔Effect of the invention〕

As explained above, the present invention is output ready.

When the input is ready, data is immediately transferred to the data receiving side from the data transmitting side that is in the output ready state and has the highest priority. Therefore, according to one aspect of the present invention, there is an effect that data can be selectively transferred from one or more data transmitting sides to one data receiving side easily and at high speed and asynchronously.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the system configuration of an example of the data selective transfer method according to the present invention, and FIG. 2 is a diagram showing the configuration of an example of the data selective transfer control circuit when the number of data transmitters is 6 (not shown). 6 are diagrams showing examples of input/output signal waveforms of main parts in the data selection transfer control circuit. 1-1 to i-N (transmission 94) FiF. 2...(Receiving side) FiF. 3-1 to 3-N... Tri-state buffer gate 4... Common parallel data transfer path 5... Data selection transfer control circuit

Claims (1)

[Claims] Based on the premise that there is a data output ready signal outputted from either of the data transmission sides each having a first-in-first-out storage means, and a data input ready signal outputted from the data reception side each having a first-in-first-out storage means, Receive data from the data transmitter with the highest priority among the data transmitters that issued the data output ready signal via the common data transfer path! 1
A data selective transfer method characterized by instructing illJ to take in data and selectively transferring transmitted data to a data receiving side by prompting a data transmitting side related to data output to shift out data.