JP2754107B2 - Data transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus, and more particularly, to a data transmission apparatus for transmitting data between apparatuses using a handshake technique.

[0002]

2. Description of the Related Art In a first-in first-out (FIFO) or data-driven information processing apparatus, a data transmission apparatus using a handshake circuit is used.

FIG. 3 is a block diagram showing an example in which a plurality of data transmission lines are connected, and FIG. 4 is a diagram showing an example of a data transmission line using a conventional handshake circuit.

First, referring to FIG. 3, a plurality of data transmission lines 10, 20, 30 are connected in series, and each data transmission line 1
0, 20, and 30 are transfer control circuits 11, 21, 3, respectively.
1 and data holding circuits 12, 22, and 32. Each of the transfer control circuits 11, 21, 31 transmits the data held in the data holding circuits 12, 22, 32 to the subsequent data transmission path if these data transmission paths are empty. The transmission signals C20, C30, and C40 are provided from the transfer control circuits 11, 21, and 31 to the transmission control circuit in the subsequent stage, and the transmission permission signals AK10, AK20, and A are transmitted to the transfer control circuit in the preceding stage.
Give K30.

Next, the transfer control circuit 21 will be described in more detail with reference to FIG. The transfer control circuit 21 is NOR
Gates G11 and G12, NAND gate G13, and N
NOR gates G14 and G15 forming an OR latch;
Inverters 16 and G17 and buffers G19 and G20 are included.

FIGS. 5 and 6 are timing charts for explaining the operation of the data transmission line shown in FIG. next,
An operation of transmitting data from the data transmission line 10 to the data transmission line 20 when there is no data on the data transmission line 20 will be described with reference to FIG. When the clock signal φ _{m +1} as shown in FIG. 5A is applied to the transfer control circuit 21 of the data transmission line 10, the transfer control circuit 11 sends the transfer control circuit 21 a signal shown in FIG. Such a transmission signal C20 is provided. This transmission signal C20 is applied to one input terminal of a NOR gate G11 of the transfer control circuit 21,
An "L" level signal is output from the output terminal, and a transmission permission signal A as shown in FIG.
K20 is supplied to the transfer control circuit 11 and inverted by the inverter G16, and supplied to the data holding circuit 22 as a clock signal. The transfer control circuit 11 of the data transmission line 10 supplies the data held in the data holding circuit 12 to the data holding circuit 22 of the data transmission line 20 according to the transmission permission signal AK20 given from the transfer control circuit 21. The data holding circuit 22 holds data from the data transmission line 10 according to the clock signal given from the transfer control circuit 21.

Next, referring to FIG. 6, data transmission path 30
The operation of transmitting data from the data transmission path 20 to the data transmission path 30 when there is no data in the data transmission path will be described. FIG.
As shown in FIG. 6A, when the clock signal φ _{m -1} is applied to the transfer control circuit 31, the transfer control circuit 31 gives the transfer control circuit 21 an "H" level as shown in FIG. Is given. This transmission permission signal AK30 is supplied to the AND gate G1 of the transfer control circuit 21.
3 is provided to one input terminal. Clock signal φ _m-1
From the clock signal φ shown in FIG.
_m is applied to an AND gate G13 of the transfer control circuit 21, and is inverted by an inverter G17 and applied to a NOR gate G15. AND gate G13 in response to the "H" level of the clock signal phi _m, giving a "H" level signal shown in FIG. 6 (g) to the NOR gate G14. As a result, NO composed of NOR gates G14 and G15
The R latch is latched, the output of the NOR gate G14 goes to "L" level as shown in FIG. 6 (h), and the output of the NOR gate G15 goes to "H" level. This "H" level signal is applied to NOR gate G12 and to transfer control circuit 31 as transmission signal C30 via buffer G20. NOR gate G12 provides an "L" level signal to NOR gate G11 in response to the "H" level signal output from NOR gate G15. And NO
An "H" level signal is output from the output of the R gate G11, and a transmission permission signal AK20 as shown in FIG. 6D is output via the buffer G19. When clock signal φ _m falls to "L" level, the output of inverter G17 is inverted, the NOR latch between NOR gates G14 and G15 is reset, and transmission output signal C30 attains "L" level.

FIG. 7 is a diagram showing an example in which a plurality of data transmission paths are connected to form a pipeline. Referring to FIG. 7, a first transmission line is formed by data transmission lines 10 and 20 shown in FIGS. 3 and 4, connected to junction 110, and a second transmission line is formed by data transmission lines 30 and 40. And is connected to the junction 110. The merging section 110
The data transmitted from the first and second transmission paths are merged, and the merged data is transmitted to the branching unit 120 via the data transmission paths 50 and 60. The branching unit 120 is for branching transmitted data,
The signal is branched into a third transmission path including the data transmission paths 70 and 80 or a fourth transmission path including the data transmission paths 90 and 100. Of the transmission paths, 10, 3 of the data transmission on the input side
0,50,70,90 clock signal phi _A is given to, the clock signal phi _B is applied to the data transmission path 20,40,60,80,100. Each data transmission line has a clock signal φ _A , if the subsequent data transmission line is in an idle state.
When any of φ _B is given, the data is given to the subsequent data transmission path.

[0009]

When the data transmission apparatus shown in FIG. 7 is formed by one integrated circuit, it is often the case that the buffer 130, A signal is output to the outside through 140. However, in the example shown in FIG. 7, since the data transmission line 80, 100 as two output ports clock pulses phi _B of the same phase are given, there is the data of the two output ports change simultaneously . For this reason, switching noise generated by switching the output buffers 130 and 140 at the same time increases. When this switching noise is mixed into the power supply or the ground, it adversely affects other circuit elements and may cause a malfunction.

[0010] Therefore, a main object of the present invention is to provide a data transmission apparatus which can directly connect data transmission apparatuses and can suppress switching noise while improving expandability.

[0011]

SUMMARY OF THE INVENTION The present invention is a data transmission apparatus for transmitting data given from a preceding stage to a succeeding stage in response to first and second clock pulses having different phases. A first data transmission path for transmitting data according to a clock pulse, a second data transmission path for transmitting data according to a second clock pulse, and a preceding data transmission path corresponding to the first clock pulse Selecting means for providing the data to the second data transmission line when outputting data in response to the second data transmission line, and selecting the first data transmission line when the preceding data transmission line outputs data in response to the second clock pulse. And is provided.

[0012]

In the data transmission apparatus according to the present invention, when the preceding data transmission path outputs data in response to the first clock pulse, the data is supplied to the second data transmission path, and the preceding data transmission path is supplied to the second data transmission path. When outputting data according to the second clock pulse, by selecting the first data transmission path, when two data transmission paths for output are provided in parallel, data is output according to different clock pulses. It is transmitted and switching noise can be reduced.

[0013]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an input data transmission line shown in FIG.

Referring to FIG. 1, input section data transmission paths 150 and 160 are connected in parallel to junction section 110, and first and second clock signals are respectively connected to input section data transmission paths 150 and 160. φ _A and φ _B are given. Merging 1
Data transmission lines 50 and 60 are provided between 10 and the branching unit 120 in the same manner as in FIG. 7 described above, and different clock signals φ _A and φ _B are provided. The branch unit 120 includes a data transmission path 70 and a data transmission path 90,
100 are connected in parallel. Clock signal φ _A is applied to data transmission lines 70 and 90, and data transmission line 1
The clock signal φ _B is given to the 00. That is, in the embodiment shown in FIG. 1, only one data transmission line 70 provided with the clock signal φ _A is provided on one transmission line, and the clock signal φ is provided on the other transmission line.
A data transmission path _{100 A} and the data transmission line 90 given the clock signal phi _B is provided is provided.

The input unit data transmission line 150, as shown in FIG. 2, the data transmission path 19 to the clock signal phi _A is given
0 and a data transmission line 210 to which a clock signal φ _B is applied.
And selectors 180 and 200. The data transmission line 100 on one side of FIG.
In the same manner as shall be only the data transmission line 170 to the clock signal phi _B given are connected. An output signal SL1 is output from the data transmission path on the output side. This output signal SL1 is set to the "H" level when the clock signal phi _A is applied to the data transmission path 170 of the output side, when the clock signal phi _B is given "L"
Set to level. This output signal SL1 is the selection signal S
It is given to selectors 180 and 200 as L2. When the selection signal SL2 is at the “H” level, the selector 180 outputs the data 1 from the output-side data transmission line 170 and the transmission signal C
1 when the selection signal SL2 is at the “L” level,
The data 2 from the data transmission path 190 and the transmission signal C2 are selected. The selection signal of the selector 180 is given to the data transmission line 110 as data 3 and a transmission signal C3. Data transmission path 210 and outputs the data and the transmission signal in response to the clock signal phi _B. The selector 200 selects the transmission permission signal R3 from the data transmission line 210 when the selection signal SL2 is at “H” level, and selects the transmission permission signal R2 from the data transmission line 190 when the selection signal SL2 is at “L” level. . The selected output of the selector 200 is supplied to the output-side data transmission path 170 as a transmission permission signal R1.

As described above, the data transmission path 17 on the output side
Or a clock signal applied to the 0 is phi _A or phi
Depending on whether the _B, the data transmission path 2 which operates the data from the output side of the data transmission path 170 by the clock signal phi _B
10 or the output side data transmission path 170
Data supplied to the data transmission line 190 which operates by the clock signal phi _A and from, by switching the selector 180 to provide the output to the data transmission line 210, the output side of the data to be operated by the clock signal phi _A or phi _B By providing a transmission line, not only the occurrence of switching noise can be reduced, but also the system can be easily expanded.

[0017]

As described above, according to the present invention, when the preceding data transmission line outputs data in response to the first clock pulse, the data transmission for transmitting data in response to the second clock pulse is performed. When the data transmission path of the preceding stage outputs data in response to the second clock pulse, the first data transmission path transmitting data in response to the first clock pulse is selected. Because
The number of output buffers that are switched at the same time can be reduced, and switching noise can be reduced. Further, even when data transmission devices of the same type are connected to each other, a data transmission device with good expandability can be obtained without being limited by the difference in the phase of the clock signal.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an input unit data transmission line shown in FIG.

FIG. 3 is a schematic block diagram of a data transmission device in which a plurality of data transmission paths are connected in series.

FIG. 4 is a specific block diagram of a transfer control circuit included in the data transmission path shown in FIG.

FIG. 5 is a timing chart for explaining an operation of transmitting data from the data transmission line 10 to the data transmission line 20 when no data exists on the data transmission line 20 shown in FIG.

FIG. 6 is a timing chart for explaining an operation of transmitting data from the data transmission path 20 to the data transmission path 30 when no data exists in the data transmission path 30 shown in FIG. 3;

FIG. 7 is a block diagram showing an example in which a plurality of data transmission paths are connected to form a pipeline.

[Explanation of symbols]

50, 60, 70, 90, 100, 170, 190, 2
Reference Signs List 10 data transmission line 110 junction unit 120 branch unit 150, 160 input unit data transmission line 180, 200 selector

──────────────────────────────────────────────────続 き Continuation of front page (51) Int.Cl. ⁶ identification code FI G11C 19/00 G06F 15/16 310D (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/82 G06F 13 / 42 G06F 15/16 G11C 7/00 G11C 19/00 JICST file (JOIS)

Claims (1)

(57) [Claims] A first and a second phase having different phases;
A data transmission device for transmitting data provided from a preceding stage to a subsequent stage in response to a clock pulse of: a first data transmission path for transmitting data in response to the first clock pulse; The second data transmission path for transmitting data in response to the clock pulse and the data transmission path at the preceding stage are the first data transmission path.
When outputting data in response to the clock pulse of the second data transmission path, applying the data to the second data transmission path, and outputting the first data when the preceding data transmission path outputs data in response to the second clock pulse. It is provided with selection means for selecting the first and second data transmission paths so as to provide the data to the transmission path.