JPS6084626A - Keyboard circuit - Google Patents

Abstract

PURPOSE:To obtain highly reliable data at low cost by outputting a status signal during the depression of a key SW in consideration of a trigger of a data latch circuit. CONSTITUTION:Pulses from an oscillator 4 are received by a decoder 3 and a scan decode 2 is driven to scan an SW matrix 1, line by line. When some key is hit, its code is inputted to a decoder 5 with priority and the scanning of the scan decoder 2 is stopped through the decoder 3. The data is inputted to a timer 6 and then a signal is sent to a depression status circuit 12 and a start latch 8. Further, a trigger is supplied from a read input circuit 11 to the start latch 8 with a read signal, and said latch 7 and start latch 8 are reset with a reset signal to fetch data. This operation is repeated continuously plural times and only when data has the same code, the data is judged as correct data and accepted by an external circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is intended to capture only reliable data from the keyboard at high speed in a system that makes full use of the keyboard.

[Prior art]

Conventionally, there has been a keyboard of this type as shown in FIG. In the figure, (1) is a 5w matrix, (2)
is a scan decoder, (3) is a decoder, (4) is an oscillator, (5) is a decoder with priority, and (6) is s
w is the chattering timer, (7) is the data latch,
(8) is a startup latch, (9) is a buffer, and σQ is a data capture completion generation circuit. Note that T in the figure means a trigger, and R means a reset input.

In the device configured in this way, the oscillator (4)
)t<μ is output, the decoder (3) receives this pulse, the scan decoder (2) is fully driven, and the SW matrix (1) 'e is activated one by one in turn, and if it is activated, press the down key on the activated column. If there is, that code is input to the priority decoder (5), and since some key has been pressed, the priority decoder (5) sends a signal to the decoder (3) and scans the scan decoder (2). Stop scanning. At the same time, the SW chattering is input to the full-load timer (6), and the data is latched after the timer (7).
and sends a signal to the activation latch (8) for OK to read the key SW data. The startup latch (8) is reset by an external circuit seeing the output of the startup latch (8), reading the data in the data latch (7), and then inputting a signal to the data capture completion generation circuit QO. .

This will return you to the initial state.

Conventional keyboard circuits are configured as described above, so in principle, the data does not change when the data is latched, and in the unlikely event that the key is pressed again or released, the latch timing will change. If they overlap, there is a possibility that a key code that has not been pressed will be latched as data, which is a major drawback.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is a complete combination of the following: ■ The status that the key is pressed down, and ■ The data latch is performed at the timing of external reading. This paper proposes a complete keyboard circuit that can determine whether the data is correct or incorrect by alternately looking at , and multiple times, and can input data only if it is correct.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. Second
In the figure, (1) to (9) are the same as in FIG. 1, (Ill is a read input circuit, (l'i> is a lowering status circuit).

(The river is the input read signal from the outside, (7T) is the trigger signal for the data latch (7) generated in the read input circuit (Ill), (7R) is the trigger signal for the data latch (7) and the start latch (8). This is a reset signal.

In addition, in FIG. 3, (Ill is the input read signal, (7
T) is a trigger signal, and (7R) is a reset signal.

Next, the operation of the embodiment of this invention will be explained.

A bus is output from the oscillator (4), and this pulse is received by the full decoder (3), which drives the scan decoder (2).
Activate each t-1 column of the W matrix (1) in order, and if there is a down key in the activated column, that code is input to the decoder with 1 priority (5), which means that some key was pressed down. Decoder with priority (5
) sends a signal to the decoder (3) and scans the decoder (2).
) to stop scanning. At the same time, considering SW chattering, a signal is input to the timer (6), and after the timer, a signal is sent to the lowering status circuit (12) and the start latch (8) of the key SW data reading member, and the output of this start latch (8) is sent to the outside. When the circuit sees the external circuit, first the lower status circuit (+21 output all prefectures, read signal Fill 'r,
It is input to the read input circuit (11), the (7T) signal is generated at the falling edge of the (Ill signal), a trigger is given to the data latch (7), and the reset signal (7R )ff is generated and the data latch (7) and startup latch (8) are reset.

At this time, when the first input read signal (II) rises, the reset signal (7R'rC start latch (8) is reset). After that, the status of the lower status circuit θ is read again and the read signal is output. Input the data by inputting it.If you return it multiple times in a row at a fast time, it will be useful.If the status is low all the time and the data at that time is the same code. only, the data is determined to be correct, and the external circuit accepts the data.If
If the status is not under medium pressure multiple times, or if it is under pressure but the data codes do not match, it will be treated as an error υ data code and the data will not be imported. If it is under compression and the data code continues multiple times, the entire data will be absorbed. Further, while the rolling down signal is being input, lead input continues to be input from the outside.

In any case, once the correct data and incorrect 9 data have been determined, the data is reset to the initial state and the primary key is ready for listening.

Note that in the above embodiment, the timer (6) is replaced by the oscillator (4).
Although the diagram shows an asynchronous case, it may also be synchronous.

Further, although the lowering status circuit output (121) is shown as a signal different from the data, it may be applied to one bit of the data by changing the address with the data latch (7).

〔Effect of the invention〕

As described above, according to the present invention, the trigger of the data latch circuit is taken into consideration and the status signal while the key SW is being pressed is output (14 times) so that the 9 times of reading can be arbitrarily determined by software. Therefore, as a keyboard, extremely reliable data can be obtained at low cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional keyboard circuit, Figure 2 is a block diagram showing a conventional keyboard circuit.
FIG. 3 is a block diagram showing a keyboard circuit R according to an embodiment of the present invention, and FIG. 3 is a waveform diagram showing one signal waveform in an embodiment of the present invention. (1)...SW matrix, (2)...scan decoder, (3)...decoder, (4)...oscillator, (5)...priority-1 (6)...° timer With decoder, (7)...data latch, (8)...
Start latch, (9)...Buffer % (11)...Lead input port F15, (121...Down status circuit, (Ill...Input read signal, (7T)...Trigger signal, (7R )... Reset signal In the figures, the same reference numerals are the same or (゛ indicates the target part. Agent Masuo Oiwa Figure 1)

Claims (1)

[Claims] It is equipped with a circuit that can latch the status signal and read signal that are output while the switch is pressed, and the data can be taken in multiple times, and the data is determined to be correct or incorrect, and the data is adopted only if it is correct. A keyboard circuit featuring: