JP3078194B2 - Key scan circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key scan circuit used for a telephone or the like, and more particularly to a key scan circuit which is effective for reducing power consumption and for an apparatus in which chattering in a switch portion having a key matrix structure becomes a problem. It relates to a scan circuit.

[0002]

2. Description of the Related Art In a conventional key scan circuit, in order to determine that a key in a key matrix has been pressed,
A key scan was performed periodically, and a specific current was constantly consumed (see FIG. 3). Further, keys may be erroneously recognized due to chattering in the switch section having the key matrix configuration.

A conventional key scan circuit will be described below with reference to the drawings. FIG. 4 is a block diagram of a conventional key scan circuit. In FIG. 4, reference numeral 7 denotes a shift register having n outputs and 8 denotes an input latch circuit having m inputs. The shift register 7 and the input latch circuit 8 constitute an n × m key matrix 12. Reference numeral 9 denotes a pulse generation circuit, which includes a shift register 7 and an input latch circuit 8.
And a pulse signal to the counter 10. Reference numeral 11 denotes a determination circuit which determines the output of the counter 10 and the output of the input latch circuit 8, and outputs output data and a signal indicating that a key has been pressed.

The operation of the conventional key scan circuit configured as described above will be described below with reference to FIG. First, out of the n outputs of the shift register 7, only one of them is active, and the other n-1 outputs are non-active. The output in the active state is sequentially shifted by using the output of the pulse generation circuit 9, and the states of m input lines crossing the output line in the active state are input to the input latch circuit 8. The output of the pulse generation circuit 9 is also input to the counter 10 so that the key matrix 12
Of the n output lines in the active state are counted. The determination circuit 11 determines which key of the key matrix 12 has been pressed from the output of the counter 10 and the output of the input latch circuit 8, outputs the data as data, and outputs a key press signal (an interrupt signal to the CPU).

[0005]

However, in the operation described above, even when no key is pressed, a key scan operation (see FIG. 3) is performed periodically, and a key matrix is formed. Only after all the switches have been scanned, it is determined that no key has been pressed. That is, even when the key is not pressed (in most cases), the key scan operation needs to be performed periodically, and a specific current is always consumed. When used in a device that is expected to consume low power, such as a portable device driven by a battery, the current consumption is a problem. In addition, since chattering occurs in the switch unit having the key matrix configuration (see FIG. 3), if only one key scan operation immediately after the key is pressed overlaps with the chattering period, which key is pressed due to its influence. There is also a problem that a wrong recognition is made when judging.

An object of the present invention is to provide a key scan circuit which solves the above-mentioned problems, minimizes the current to be dissipated, and can eliminate the influence of chattering of the switch section and improve the reliability of scanning. Aim.

[0007]

In order to solve the above-mentioned problems, a key scan circuit according to the present invention comprises a key scan circuit which operates when a key is not pressed in order to minimize current consumption by the key scan operation. Is stopped, and an interrupt signal is generated for each state when any key is pressed, while it is being pressed, and when it is released, so that the state of each key switch is changed to CP.
U to recognize the key, perform the key scan operation only when an interrupt signal is generated while the key is being pressed, and have an internal timer to prevent the key from being erroneously recognized due to chattering of the key pressing switch. During this time, the CPU periodically generates an interrupt signal at a preset timer time interval (time considering the chattering time) so that the CPU performs the key scan operation by software. It was made.

[0008]

Therefore, in the circuit according to the present invention, there is no change in the signal in the circuit in the key input waiting state, and the consumed current is minimized. In addition, scanning is performed after a periodic interrupt signal is generated by a timer that can be arbitrarily set in consideration of a chattering time having different characteristics for each switch, so that there is less danger of malfunction due to chattering.

[0009]

FIG. 1 is a block diagram of a key scan circuit according to an embodiment of the present invention. Hereinafter, a configuration example of the present invention will be described with reference to the drawings. In FIG. 1, 1 is a key scan register for n outputs and 2 is a key sense register for 2 inputs. The key scan register 1 and the key sense register 2 form n × m key matrices 3. Be composed. Reference numeral 4 denotes an interrupt determination / generation circuit which determines the state of m input lines of the key matrix 3
When any key is pressed, while it is being pressed, and when it is released, an interrupt signal is generated for each state. Reference numeral 5 denotes an interrupt status circuit, which indicates information indicating permission / inhibition of generation of an interrupt signal, information indicating control of a timer provided in the interrupt determination / generation circuit 4, information indicating cancellation of an interrupt signal, and information of an interrupt signal. Information for recognizing the state is provided. 6 is a pull-up resistor for m input lines.

The operation of the above configuration will be described below with reference to the timing chart of the key scan processing in FIG. By enabling generation of a push interrupt signal (FIG. 2: push interrupt enable flag ON state) by the interrupt status circuit 5 of FIG. 1, the interrupt determination / generation circuit 4 is enabled to generate a push interrupt (waiting for key input). become.

In the key input waiting state, all the n output lines from the key scan register 1 are active. Here, when any key is pressed, one of the m input lines to the key sense register 2 becomes active, and the interrupt determination / generation circuit 4 determines that the key has been pressed, and , A push interrupt signal (FIG. 2: push interrupt signal) is generated.

The CPU receives the push interrupt signal and starts the software processing. The interrupt status circuit 5 reads information indicating the state of the push interrupt signal, and recognizes that the signal generated by the interrupt determination / generation circuit 4 is a push interrupt signal. Subsequently, data is written to the interrupt status circuit 5, and the generation of a key press interrupt signal by another key in the interrupt determination / generation circuit 4 is prohibited (hereinafter, until the generation of the key press interrupt signal is enabled again, the other key press interrupt signal is generated). The generation of the push interrupt signal is prohibited, and the generation of the timer interrupt signal is enabled (FIG. 2: the push interrupt enable flag is OFF), and the timer interrupt signal can be generated in the interrupt determination / generation circuit 4. FIG. Interrupt enable flag O
After N state), the timer start information is activated (FIG. 2:
Set the timer start flag ON) and clear the push interrupt signal.

When the timer activation information becomes active, the timer in the interrupt determination / generation circuit 4 is activated, and a predetermined time is set for a predetermined timer time interval (time interval considering switch chattering). Later, a timer interrupt signal (FIG. 2: timer interrupt signal) is generated for the CPU.

The CPU receives the timer interrupt signal and enters a software process. The interrupt status circuit 5 reads information indicating the state of the timer interrupt signal, and recognizes that the signal generated by the interrupt determination / generation circuit 4 is a timer interrupt signal. Subsequently, the CPU performs a key scan process (writes data to the key scan register 1 and sequentially activates one of the n output lines one by one, and determines the state of the key switches arranged in a matrix from the key sense register 2 by the key sense register 2). A key code is recognized by reading each time, and the key code is stored.
Thereafter, data is written to the interrupt status circuit 5, and the generation of the timer interrupt signal in the interrupt determination / generation circuit 4 is inhibited (the generation of the timer interrupt signal is inhibited in the interrupt determination / generation circuit 4. FIG. 2: Timer The interrupt enable flag is OFF), and the generation of the key release interrupt signal is enabled (a remote interrupt signal can be generated in the interrupt determination / generation circuit 4. FIG. 2: The remote interrupt enable flag is ON), and the timer interrupt signal is set. clear.

Since the generation of the key release interrupt signal is permitted, the key release wait state is set. When the key is released, the interrupt determination / generation circuit 4 generates a remote interrupt signal (FIG. 2: remote interrupt signal) to the CPU.

The CPU receives the remote interruption signal and enters a software process. The interrupt status circuit 5 reads information indicating the state of the remote interrupt signal, and recognizes that it is a remote interrupt signal. Subsequently, data is written to the interrupt status circuit 5, and the generation of the key release interrupt signal is prohibited (the generation of the release interrupt signal is prohibited in the interrupt determination / generation circuit 4. FIG. 2: The release interrupt enable flag is OFF).
After enabling generation of a key press interrupt signal (a press interrupt signal can be generated in the interrupt determination / generation circuit 4. FIG. 2: Press interrupt enable flag ON), the key release interrupt signal is cleared, and the initial state ( Key input).

Further, as another usage example, the key scan process is performed n times by generating the timer interrupt signal while the key is being pressed, not only once, but n times. It is also possible to make the software such that

The above-described embodiment shows an example of the present invention, and the present invention is not limited to this.

[0019]

As described above, according to the present invention, the key scan operation is performed only when the timer interrupt signal is generated while the key is pressed, so that the current consumption can be minimized as compared with the prior art. Can be. Further, since the key scan operation is performed at fixed time intervals (arbitrarily determinable) by the timer interrupt signal, chattering of the switch unit can be eliminated (see FIG. 2), and the reliability of scanning can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a key scan circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of hardware processing and software processing in the key scan circuit according to one embodiment of the present invention;

FIG. 3 is a comparison diagram of a conventional key scan operation interval and a key scan operation interval according to the present invention.

FIG. 4 is a block diagram of a conventional key scan circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 key scan register 2 key sense register 3 key matrix 4 interrupt determination / generation circuit 5 interrupt status circuit 6 pull-up resistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 3/023 G06F 3/02 320

Claims (2)

(57) [Claims] In a key scan circuit for detecting a key state, an interrupt determination for generating an interrupt signal for each state when any key is pressed, while it is being pressed, and when it is released / Generating circuit, and an interrupt status circuit having information indicating a state of the interrupt signal and information indicating permission / inhibition of generation of the interrupt signal, and only when an interrupt signal is generated while the key switch is pressed. A key scan circuit which performs a key scan operation. 2. An interrupt judging / generating circuit is provided with an internal timer so that an interrupt signal can be periodically generated while a key switch is pressed, and the time of the timer can be arbitrarily set. The key scan circuit according to claim 1, wherein