JPS6081951A - Fsk demodulator - Google Patents

Abstract

PURPOSE:To simplify the constitution of an FSK demodulator and eliminate variation in an output level depending upon the pattern of a data signal by providing a logical circuit consisting of plural FF circuits, an NAND circuit, a counter, etc. CONSTITUTION:A receive signal 3 is read in a receive signal read-in FF9 inputting the output of the FF9 to a shifting FF10 to be shifted. A clock signal 4 is supplied to the FFs 9 and 10, whose outputs are NANDed by an NAND circuit 11 to output a clear pulse 7. This clear pulse 7 is applied to a counter 12 and an FF14 for counter control. The counter 12 counts a clock signal 4 and outputs a ripple carrier output pulse 8. The output pulse 8 of the counter 12 is applied as a clock to an FF13 for data reproduction and also applied to the FF14 after being inverted. The output of the FF14 is applied to the counter 12, which stops counting temporarily from the generation of the output pulse to the generation of the next pulse 7 to prevent the variation in an output level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FSK demodulator that completely demodulates a signal into frequency-modulated P8 using two-frequency signals having different frequency sounds that are integral multiples of a data rate.

The signal F8 is a two-frequency signal corresponding to each of the marks M and spaces S of the data signal to be transmitted, and is switched at a change point of all transmitted data. Note that, from the viewpoint of effective band utilization, it is common that the two-frequency signal is switched to have a continuous phase at a data change point.

Conventional FSK demodulators include a frequency-discriminating demodulator with two tuning circuits, a zero-crossing demodulator that obtains an output proportional to the frequency at which the FSK modulation signal becomes zero, and a frequency-discriminating demodulator with an FSK modulation signal delayed by a certain period of time. There is a delay demodulator that outputs the data signal from the product of the signal and the current FSK modulation signal. Both methods require the entire low-frequency F-wave device to extract only the data signal, and have the disadvantage that the output level of the low-frequency F-wave device varies depending on the pattern of the data signal.

An object of the present invention is to provide an easy-to-use FSK signal that does not have output level fluctuations depending on the data signal pattern and uses only logic circuits.
The purpose of the present invention is to provide a demodulator.

The FSK demodulator of the present invention uses an FSK modulated signal using a two-frequency signal combination having different frequency sounds that are integral multiples of the data signal rate. The first flip-flop that receives and reads it as reception number 4, and the output of the first flip-flop as input. A second flip-flop to shift, a gate circuit which uses the output of the second flip-flop and the output of the first flip-flop as all inputs, and an output of the gate circuit? A third flip-flop that uses the ripple carry output pulse of the counter as a clear pulse and the output sound of the gate circuit as reset and set inputs, respectively, and a third flip-flop that uses the ripple carry output pulse of the counter as a total tally signal. It has a fourth flip-flop and gold with all inputs as outputs.

Figure 1 is a timing diagram for explaining general FSK modulation.
Two frequency signal stations used for fx=m7fb and f2, respectively
=n-fb. However, it is 2m.

n is an integer and n)m. Further, it is assumed that the received signal 3 of this demodulator is phase-controlled and switched by the transmitter so that the rising edge of fl or f2 occurs at the changing point of the data signal. 1 is a reception timing signal.

Next, embodiments of the present invention will be described. As shown in FIG. 2, the received signal 4 3 is taken into the demodulator by a D-type flip-flop 9, and its output 5 is controlled to be cleared at the rising point of the received signal 4 3 and to start counting completely. The ripple carry output pulse 8 of the counter 12 is read again by the final stage type flip-flop 13 as a clock signal, and the data signal 2 is reproduced. Incidentally, the D-type flip-flop 10 and the NAND circuit 11 receive all the clear pulses 7 for completely clearing the counter at the rising edge of the reception signal No. 4.

A D-type flip-flop 14 and a NAND circuit 15 output a ripple carry output pulse 8 and a clear pulse 7 of the counter.
They are used for reset and set inputs, respectively, and are used to temporarily stop the entire counter after the ripple carry pulse 8 is generated until the next clear pulse 70 is generated.

Next, the operation of the demodulator at F8 will be explained with reference to FIG. Frequency 2 of counter clock signal 4 f o
= 2amnfb. However, a is an appropriate integer. Therefore, a half period of the received signal 3 with one frequency f1 corresponds to an period of the clock signal 4, and a half period of the received signal 3 with one frequency f2 corresponds to an period of the clock signal 4.
Similarly, the half cycle corresponds to the am cycle of the clock signal 4. If the number of stages of the counter 12, which is controlled to start counting at the rising edge of the received signal 3, is set around (am+an)/2 and the ripple carry output pulse 8 is used to read all of the received signal 3, the received signal 3 with the frequency f1 is read. Then, it is always the first half of one cycle, that is, the entire high level, -10,000.

The received signal 3 of frequency f2 always reads the second half of one cycle, that is, the Wachiro V Bell meeting (see the broken line). In this way, data signal 2 is reproduced.

For convenience of explanation, in FIG.
(n = 3) and fo = 12fb (a = 1), all frequencies were set simply, but in reality, the received signal and clock signal are originally asynchronous, so select a clock signal with an arbitrary frequency t that does not affect operation. can do. If the frequency of the clock signal relative to the received signal is too low, the received data will have a lot of jitter. Therefore, when setting the frequency of the clock signal, consider the required jitter rate and the circuit elements used, and set the appropriate frequency range. should be selected.

As is clear from the above explanation, the number of stages f of the VC% counter
(am+a n )/2, that is, if the period f f of the ripple carry output pulse of the counter is selected as the average of the half periods of 1 and f2, various noises or frequencies f1 and f2
The fluctuation in the pulse width of the received signal caused by the relative frequency difference between the received signal of f and the clock signal of the demodulator causes the clock signal f
The data signal can be completely reproduced within a(n-m)/z period of O.

As described above, according to the present invention, a simple demodulation circuit can be constructed using only logic circuits.

[Brief explanation of the drawing]

Figure 1 is a time chart that fully explains general FSK modulation.
FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing the operation of FIG. 2...Data signal %3...Received signal,
4...Clock signal, 7...Clear pulse, 8...Ripple carry output pulse, 9
・・・・・・Received M double number reading flip-flop, 10
...Flip-flop for shift, 11...
・・NAND times L 12------Counter, 13・
...-Flip-flop for data reproduction, 14...
...Counter control flip-flop. ,':', Agent: Susumu Uchihara, Patent Attorney, ('') Graduated from 1st year of graduation 2nd time~Left

Claims (1)

[Claims] 2 with mutually different frequencies that are integral multiples of the data signal rate
a first flip-flop that receives a modulated signal sound at F8 using a frequency signal and reads it as a received signal; a second flip-flop that receives the output of the first seven-lip flop and shifts it entirely; a gate circuit that uses the output of the flip-flop and the output of the first seven lip-flops as input; a counter that uses the output of the gate circuit as a clear pulse; and a ripple carry output pulse of the counter and the output t of the gate circuit, respectively. An FSK demodulator having a third flip-flop as a set input, and a fourth flip-flop having as an input the output of the first seven flip-flops as the ripple carry output pulse of the counter as a full clock signal.