JPS6081919A - Programmable digital window comparator - Google Patents

Abstract

PURPOSE:To decide on data excellently with simple circuit constitution by updating plural measured data sent to an upper-limit and a lower-limit comparing circuit in order, and comparing them with corresponding upper-limit and lower-limit threshold value data. CONSTITUTION:Plural kinds of measured input data 1 are updated and sent to one-side input terminals of the upper-limit and lower-limit comparing circuits 10a and 10b successively. Further, upper-limit and lower-limit threshold value data 4a and 4b are supplied from upper-limit and lower-limit storage circuits 12a and 12b to the other-side input terminals of those circuits 10a and 10b, which compare the data 1 with the threshold value data respectively. When the data 1 is updated, a counter-up signal 2 is generated synchronously and an output count value signal 3 obtained by adding ''1'' to the current value is sent from a counter 11 to the circuits 12a and 12b to supply corresponding threshold value data 4a and 4b to the circuits 10a and 10b, so that the corresponding data 1 are compared with the threshold value data 4a and 4b.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable digital window comparator, and in particular, to a programmable digital window comparator that has a plurality of A programmable digital device that can determine whether or not each input data to be measured is within the corresponding setting range using one counter, two memory circuits, and two comparison circuits. Wind
Concerning comparators.

Generally, there are two ways to determine whether or not input data is within the set range. One method is to use two digital comparison circuits for A, which is compared individually, and the other method is to import the data into a microcomputer and perform calculations on a programmer.

However, in the case where there is a plurality of 11111 constant input data and the setting range varies depending on each of them, in the former method, it is necessary to prepare twice as many comparison circuits as the number of the input data to be measured. Alternatively, each time the input data to be measured changes, the corresponding upper limit and lower limit threshold data must be input to the corresponding one L limit and lower limit comparison circuits, respectively, using a microcomputer, and in the latter method, the Every time the measured human input data is updated, it is necessary to update the data between the -L limit and the lower limit (+ri) and perform calculations. It is extremely unreasonable that the latter method requires a microcomputer, and the use of a microcomputer itself becomes expensive and complicated.

The present invention has been made in view of the shortcomings of the prior art, and is a programmable digital computer that can handle multiple groups of input data to be measured using a lower limit comparison circuit and simple peripheral circuits. It is intended to provide a window comparator.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure, operation, and effects of the present invention will be described below with reference to an embodiment of the present invention shown in the accompanying drawings.

The input data l to be measured consists of a plurality of types, and is sequentially updated to each of the -1- limit and lower limit comparison circuits 10a and lOb.
It can be achieved by human power. "Second limit, lower limit comparison circuit 10a, j
Each person's power of ob has an upper limit memory circuit and a lower limit memory circuit +2a, respectively.
.

The upper limit and lower limit threshold data 4a and 4b are given from the upper limit and lower limit comparison circuits 10a and IOb, and comparison processing with the input data to be measured l is performed in the upper limit and lower limit comparison circuits 10a and IOb.

Therefore, upper limit and lower limit threshold data 4a and 4b predetermined in accordance with each of the constant input data l to be measured are stored in the above-mentioned - upper limit and lower limit storage circuits 12a and +2b for each input of the input data to be measured l. They are stored in sequentially numbered addresses according to their ranking.

Here, when the input data under test 1 is updated, a count up signal 2 is generated in synchronization with this, and the counter 11 that receives this signal increments the output count value signal 3 by l゛° from the previous value. and input them to the upper and lower limit storage circuits 12a and 12b. This output count (
The +N signal 3 is the address instruction signal 3 in the lower limit memory circuits +2a and +2b, and therefore the updated address instruction signal 3 is in the lower limit memory circuits 12a and +2b.
Therefore, the upper and lower limit threshold data 4a and 4b of the address content of the address value that is 100% larger than the previous address are set to 1-limit, and the lower limit comparison circuits 10a and 1ob
send to. As mentioned above, the second limit and lower limit threshold data 4a and 4b at this time are the limit and lower limit comparison circuit 10 when turning.
a, lOb=-1-limit, lower limit threshold data corresponding to input data to be measured l given to human power.

In the comparator circuit 10a, the comparison result is ゛A1).
1 output an upper limit comparison result signal valve carrying the information of input data to be measured 1゛ limited to constant input data 1 (or ≦) upper limit threshold data 4a゛° to "-, On the other hand, the lower limit comparison circuit lOb carries the information of "1111 constant force data l≦(<) lower limit threshold data 4b゛°no'I to "lower limit threshold data 4b<(≦) input data to be measured 1''. A result signal 5b is output.

Based on the comparison result signals of the l2 limit and the lower limit obtained in this way, the discrimination circuit 14 determines that “lower limit threshold data 4b≦(<
) Threshold data 4 limited to 1111 constant input data l≦(<)
It is determined whether or not it is a'', and a signal 6 according to ``1''1 is output. The configuration of this discrimination circuit itself can be constructed using a simple logic circuit configuration using known technology.

Covered 1! If the input data l is further updated, the uppermost address of both memory circuits storing the corresponding '2 limit and lower limit threshold data 1 will be updated by the counter II by the same operation. An update is further instructed by the increment I of the address instruction signal 3 by "l", and the corresponding upper and lower limit threshold data 4a and 4b from each address for which the update is instructed are the upper and lower limit comparison circuits 10a and 10a, jo.
b, and is compared with constant input data l to be processed 1111. By repeating such operations, it is possible to handle a plurality of input data groups to be measured using two comparison circuits and simple peripheral circuits, that is, one counter or address scanning circuit and two memory circuits. The number of input data to be measured l that can be processed is an upper limit and a lower limit storage circuit 12a.
, +2b, which is generally quite large, so it can be said that the circuit of the present invention is more effective as the number of input data l to be measured increases.

In addition, for the sake of simplicity in section -1-, it is indicated that the lower limit threshold data is stored in sequentially numbered addresses according to the input order of each human power data to be measured. If it is determined, it does not necessarily have to be a consecutive number, and the upper limit value setting memory circuit and the lower limit value setting memory circuit may be different.

In the case shown, there is only one input line for the human power data to be measured, but in the case of multiple input lines, this can be handled by interposing a well-known multiplexer on the input side. .

1-1 In short, in the present invention, with the update of a plurality of pieces of human power data to be measured that are sequentially sent to the 1-limit and lower limit comparison circuits, the addresses in the storage circuit for setting the -I-limit value and the D-limit value are updated. is instructed to update synchronously, reads the l2 limit and lower limit threshold data corresponding to the input data under test updated in - from the address for which the update was instructed, and synchronizes with the - limit and do limit comparison circuit. By sending fI1. Based on this, the discrimination processing for each measured human force data within the set range is performed, so there is no unreasonable need for comparison circuits for multiples of the number of all constant human force data as in the past, and the circuit is simple. You can achieve your goals through configuration.

[Brief explanation of the drawing]

The drawing is a schematic diagram of an embodiment of the present invention. In the figure, ■ is the input data to be measured, 2 is the count-amplifier signal, 3 is the address instruction signal, 4a and 4b are 1; each threshold value data of limit and lower limit, 5a and 5b are each comparison result signal of upper limit and F limit , lOa and lob are upper and lower limit comparison circuits,
11 is a counter; +2a and +2b are memory circuits for the second and lower limits; and +4 is a discrimination circuit.

Claims (1)

[Claims] A programmable digital RAIID system that determines whether or not each of a plurality of pieces of measured human power data falls within a set range defined by a unique limit threshold and a lower limit threshold.
A comparator, comprising: an upper limit value setting storage circuit which stores upper limit threshold data in accordance with the update of the plurality of input data to be measured which are sequentially sent to both the limit comparison and lower limit comparison comparison circuits; The lower limit where the lower limit threshold data is stored (
(Instructs to update each address in the i setting memory circuit synchronously, reads each threshold value data of upper limit and de limit corresponding to the updated input data to be measured from among the addresses for which update is instructed, - By synchronously sending the data to the upper and lower limit comparison circuits, a comparison between the plurality of input data to be measured and the corresponding upper and lower limit threshold data is obtained, and each of the upper and lower limits is compared. A programmable digital device characterized in that it outputs a determination signal based on the result signal to determine whether the input data to be measured is within the above-mentioned setting range.
Wind comparator.