JPS6079847A - 通信制御装置 - Google Patents
通信制御装置Info
- Publication number
- JPS6079847A JPS6079847A JP58186790A JP18679083A JPS6079847A JP S6079847 A JPS6079847 A JP S6079847A JP 58186790 A JP58186790 A JP 58186790A JP 18679083 A JP18679083 A JP 18679083A JP S6079847 A JPS6079847 A JP S6079847A
- Authority
- JP
- Japan
- Prior art keywords
- field
- control
- line
- line adapter
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58186790A JPS6079847A (ja) | 1983-10-07 | 1983-10-07 | 通信制御装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58186790A JPS6079847A (ja) | 1983-10-07 | 1983-10-07 | 通信制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6079847A true JPS6079847A (ja) | 1985-05-07 |
JPH0210626B2 JPH0210626B2 (enrdf_load_stackoverflow) | 1990-03-08 |
Family
ID=16194629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58186790A Granted JPS6079847A (ja) | 1983-10-07 | 1983-10-07 | 通信制御装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6079847A (enrdf_load_stackoverflow) |
-
1983
- 1983-10-07 JP JP58186790A patent/JPS6079847A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0210626B2 (enrdf_load_stackoverflow) | 1990-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR900004006B1 (ko) | 마이크로 프로세서 시스템 | |
US4181934A (en) | Microprocessor architecture with integrated interrupts and cycle steals prioritized channel | |
US4112490A (en) | Data transfer control apparatus and method | |
US5701417A (en) | Method and apparatus for providing initial instructions through a communications interface in a multiple computer system | |
US5761458A (en) | Intelligent bus bridge for input/output subsystems in a computer system | |
US4378589A (en) | Undirectional looped bus microcomputer architecture | |
CN111414325B (zh) | 一种Avalon总线转Axi4总线的方法 | |
JP2004110785A (ja) | メモリコントローラ | |
US4339793A (en) | Function integrated, shared ALU processor apparatus and method | |
JPH0543151B2 (enrdf_load_stackoverflow) | ||
US5463756A (en) | Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics | |
US6085261A (en) | Method and apparatus for burst protocol in a data processing system | |
KR900002438B1 (ko) | 프로세서간 결합방식 | |
US6157971A (en) | Source-destination re-timed cooperative communication bus | |
EP1058189B1 (en) | Microcomputer with debugging system | |
KR910001708B1 (ko) | 중앙처리장치 | |
JPS6079847A (ja) | 通信制御装置 | |
JP3431025B2 (ja) | データ転送システム | |
US20060026307A1 (en) | Method for direct memory access, related architecture and computer program product | |
JPH03271829A (ja) | 情報処理装置 | |
US6510480B1 (en) | Data transfer circuit and data processing method using data transfer circuit for handling interruption processing | |
JPS63304302A (ja) | プログラマブル・コントロ−ラ | |
JPS6019816B2 (ja) | マイクロプログラム制御アダプタ | |
EP0335502A2 (en) | Microcontroller and associated method | |
JP2000029508A (ja) | プログラマブルコントローラ |